Gather buffer management for unaligned and gather load operations
US-12411688-B2 · Sep 9, 2025 · US
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Lloyd Bryan patents
Lloyd Bryan is listed as an inventor on 90 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Lloyd Bryan |
| Total patents | 90 |
| First publication | Jul 21, 2015 |
| Latest publication | Sep 9, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Clear prefetch stream on detection of pipeline flush
US-2025130947-A1 · Apr 24, 2025 · US
Sideband instruction address translation
US-2024202127-A1 · Jun 20, 2024 · US
Gather buffer management for unaligned and gather load operations
US-2023367595-A1 · Nov 16, 2023 · US
Prioritization of threads in a simultaneous multithreading processor core
US-11775337-B2 · Oct 3, 2023 · US
Gather buffer management for unaligned and gather load operations
US-11755324-B2 · Sep 12, 2023 · US
Microprocessor that fuses load and compare instructions
US-11748104-B2 · Sep 5, 2023 · US
Processor overriding of a false load-hit-store detection
US-11687337-B2 · Jun 27, 2023 · US
Virtual cache synonym detection using alias tags
US-11650926-B2 · May 16, 2023 · US
Translation bandwidth optimized prefetching strategy through multiple translation lookaside buffers
US-11645208-B2 · May 9, 2023 · US
Recent patents
Latest publications not already listed above.
Prioritization of threads in a simultaneous multithreading processor core
US-2023061030-A1 · Mar 2, 2023 · US
Gather buffer management for unaligned and gather load operations
US-2023063976-A1 · Mar 2, 2023 · US
Processor overriding of a false load-hit-store detection
US-2023056077-A1 · Feb 23, 2023 · US
Execution elision of intermediate instruction by processor
US-2023028929-A1 · Jan 26, 2023 · US
Marking in-flight requests affected by translation entry invalidation in a data processing system
US-11537519-B1 · Dec 27, 2022 · US
Execution elision of intermediate instruction by processor
US-11537402-B1 · Dec 27, 2022 · US
Writing store data of multiple store operations into a cache line in a single cycle
US-11520704-B1 · Dec 6, 2022 · US
Prefetch store preallocation in an effective address-based cache directory
US-11520585-B2 · Dec 6, 2022 · US
Virtual cache tag renaming for synonym handling
US-11500774-B2 · Nov 15, 2022 · US
Translation bandwidth optimized prefetching strategy through multiple translation lookaside buffers
US-2022309001-A1 · Sep 29, 2022 · US
Handling oversize store to load forwarding in a processor
US-11379241-B2 · Jul 5, 2022 · US
Tracking load and store instructions and addresses in an out-of-order processor
US-11321088-B2 · May 3, 2022 · US
Tracking load and store instructions and addresses in an out-of-order processor
US-11314510-B2 · Apr 26, 2022 · US
Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operations
US-11263151-B2 · Mar 1, 2022 · US
Handling and fusing load instructions in a processor
US-2022050679-A1 · Feb 17, 2022 · US
Tracking load and store instructions and addresses in an out-of-order processor
US-2022050681-A1 · Feb 17, 2022 · US
Tracking load and store instructions and addresses in an out-of-order processor
US-2022050680-A1 · Feb 17, 2022 · US
Handling and fusing load instructions in a processor
US-11249757-B1 · Feb 15, 2022 · US
Area and power efficient mechanism to wakeup store-dependent loads according to store drain merges
US-11243773-B1 · Feb 8, 2022 · US
Microprocessor that fuses load and compare instructions
US-2022035634-A1 · Feb 3, 2022 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 90 |
| Cain Iii Harold W | 1 |
| Le Hung Q | 1 |
| Lloyd Bryan | 1 |
| Tung Shih-Hsiung | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/30043 | 61 |
| G06F9/3824 | 50 |
| G06F9/3834 | 39 |
| G06F9/3836 | 37 |
| G06F9/3851 | 35 |