Tracking load and store instructions and addresses in an out-of-order processor

Patent metadata

Field	Value
Publication number	US-11314510-B2
Application number	US-202016994070-A
Country	US
Kind code	B2
Filing date	Aug 14, 2020
Priority date	Aug 14, 2020
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

A computer system, processor, and/or load-store unit has a data cache for storing data, the data cache having a plurality of entries to store the data, each data cache entry addressed by a row and a Way, each data cache row having a plurality of the data cache Ways; a first Address Directory organized and arranged the same as the data cache where each first Address Directory entry is addressed by a row and a Way where each row has a plurality of Ways; a store reorder queue for tracking the store instructions; and a load reorder queue for tracking load instruction. Each of the load and store reorder queues having a Way bit field, preferably less than six bits, for identifying the data cache Way and/or a first Address Directory Way where the Way bit field acts as a proxy for a larger address, e.g. a real page number.

First claim

What is claimed is:

1. A computer system for processing information, the computer system comprising:
at least one computer processor comprising:
a load store execution unit (LSU) for processing load and store instructions, wherein the LSU comprises:
a data cache for storing data for use by the LSU, the data cache having a plurality of entries to store the data, each data cache entry addressed by a row representing a first portion of a first address type and a Way identified by a Way bit field, each data cache row having a plurality of the data cache Ways;
a first Address Directory to store a plurality of second portions of the first address type corresponding to the data stored in the data cache, the first Address Directory having a plurality of entries equal in number to the plurality of data cache entries, each first Address Directory entry addressed by a row and a Way where each row has a plurality of Ways, the first Address Directory having a plurality of rows and a plurality of Ways equal in number to the plurality of data cache rows and the plurality of data cache Ways, each Way in the first Address Directory corresponding to a data cache Way, identified by the Way bit field, and containing the second portion of the first address type corresponding to and identifying a location in memory where the data stored in the corresponding data cache entry is located;
a store reorder queue for tracking the store instructions in the LSU, the store reorder queue having a plurality of entries for storing information for tracking the store instructions, each store reorder queue entry having a Way bit field for identifying at least one of the group consisting of a data cache Way, a first Address Directory Way, and combinations thereof; and
a load reorder queue for tracking load instructions in the LSU, the load reorder queue having a plurality of entries for storing information to track the load instruction, each load reorder queue entry have a Way bit field for identifying at least one of the group consisting of a data cache Way, a first Address Directory Way, and combinations thereof.

2. The computer system of claim 1 , wherein the processor is configured to:
determine whether at least a second portion of an address of the load or store instruction matches one of the plurality of the second portions of the first address type stored in the first Address Directory; and
in response to the at least a second portion of an address of the load or store instruction matching one of the plurality of the second portions of the first address type stored in the first Address Directory, supply the Way bit field of the second portion of the first address type stored in the first Address Directory that matches the at least second portion of an address of the load or store instruction to the store reorder queue or the load reorder queue.

3. The computer system of claim 1 , wherein the processor is further configured to:
determine whether a first portion of the first address type of the load or store instruction matches one of the rows of the first Address Directory;
in response to the first portion of the first address type of the load or store instruction matching one of the rows of the first Address Directory, reading out each second portion of the first address type in each of the first Address Directory Ways of that matching row;
sending each second portion of the first address type read out of each of the first Address Directory Ways to a Directory Way Compare Unit;
comparing each second portion of the first address type sent to the Directory Way Compare Unit by the first Address Directory to at least a second portion of the address of the store or load instruction; and
in response to the at least a second portion of the address of the load or store instruction matching one of the second portions of the first address type sent to the Directory Way Compare Unit by the first Address Directory, supply the Way bit field of the matching second portion of the first address type stored in the first Address Directory to the store reorder queue or the load reorder queue.

4. The computer system of claim 1 , wherein the processor is configured to:
determine whether at least a second portion of an address of the load or store instruction matches one of the plurality of the second portions of the first address type stored in the first Address Directory; and
in response to the at least a second portion of the address of the load or store instruction not matching one of the plurality of the second portions of the first address type stored in the first Address Directory, allocate a data cache entry including a data cache Way to contain the data associated with the load or store instruction, and allocate a first Address Directory entry including a first Address Directory Way corresponding to the data cache entry and data cache Way.

5. The computer system of claim 4 , wherein the processor is further configured to supply the store reorder queue or the load reorder queue at least one of: (a) the data cache Way bit field corresponding to the data cache Way that was allocated; (b) the first Address Directory Way bit field corresponding to the first Address Directory Way that was allocated; and
(c) combinations thereof.

6. The computer system of claim 1 , wherein the first address type is an effective address that correlates with a second address type that identifies a physical location in a memory system.

7. The computer system of claim 1 , further comprising a second Address Directory to store a plurality of second portions of a second address type corresponding to the data stored in the data cache and corresponding to the second portion of the first address type stored in the first Address Directory, the second Address Directory having a plurality of entries equal in number to the plurality of data cache entries and to the plurality of the first Address Directory entries, the second Address Directory having a plurality of rows and Ways equal in number to the plurality of data cache rows and data cache Ways and equal in number to the plurality of first Address Directory rows and first Address Directory Ways, each Way in the second Address Directory corresponding to a data cache Way and a first Address Directory Way, identified by the Way bit field, and containing the second portion of the second address type corresponding to and identifying a location in memory where the data stored in the corresponding data cache entry is located.

8. The computer system of claim 7 , wherein the processor is configured to:
determine whether at least a second portion of an address of the load or store instruction matches one of the plurality of the second portions of the first address type stored in the first Address Directory;
in response to at least a second portion of an address of the load or store instruction not matching one of the plurality of second portions of the first address type stored in the first Address Directory, determine whether at least a second portion of the address of the load or store instruction matches at least a portion of one of the plurality of the second address type contained in the second Address Directory; and
in response to the at least the second portion of the address of the load or store instruction not matching at least one of the plurality of second portions of the second address type contained in the second Address Directory, allocate a data cache entry including a data cache Way to contain the data associated with the load or store instruction, allocate a first Address Directory entry including a first Address Directory Way corresponding to the data cache entry and data cache Way, and allocate a second Address Directory entry including a second Address directory Wa

Assignees

• IBM

Inventors

• Lloyd Bryan
• Kirchhoff Samuel David
• Chen Brian
• Fernsler Kimberly M
• Hrusecky David A

Classifications

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F12/0895

  of parts of caches, e.g. directory or tag array · CPC title

• G06F9/3824

  Operand accessing · CPC title

• G06F12/0817

  using directory methods · CPC title