Writing store data of multiple store operations into a cache line in a single cycle

Patent metadata

Field	Value
Publication number	US-11520704-B1
Application number	US-202117364495-A
Country	US
Kind code	B1
Filing date	Jun 30, 2021
Priority date	Jun 30, 2021
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

A load-store unit (LSU) of a processor core determines whether or not a second store operation specifies an adjacent update to that specified by a first store operation. The LSU additionally determines whether the total store data length of the first and second store operations exceeds a maximum size. Based on determining the second store operation specifies an adjacent update and the total store data length does not exceed the maximum size, the LSU merges the first and second store operations and writes merged store data into a same write block of a cache. Based on determining that the total store data length exceeds the maximum size, the LSU splits the second store operation into first and second portions, merges the first portion with the first store operation, and writes store data of the partially merged store operation into the write block.

First claim

What is claimed is:

1. A method for writing store data of multiple store operations into a cache memory, said method comprising:
determining whether or not a second store operation specifies an update to a byte adjacent to a byte to be updated by a first store operation;
based on determining that the second store operation specifies the update to the byte adjacent to the byte to be updated by the first store operation, determining whether or not the total length of store data of the first and second store operations exceeds a maximum write block size of a cache line;
based on determining that the total length of the store data of the first and second store operations does not exceed the maximum write block size of the cache line, merging the first and second store operations to obtain a fully merged store operation and writing store data of the fully merged store operation into a same write block of the cache line; and
based on determining that the total length of the store data of the first and second store operations exceeds the maximum write block size of the cache line,
splitting the second store operation into first and second portions;
merging the first portion of the second store operation with the first store operation to obtain a first partially merged store operation; and
writing store data of the first partially merged store operation into the same write block of the cache line within the cache memory.

2. The method of claim 1 , wherein the method further includes
merging the second portion of the second store operation with a third store operation to obtain a second partially merged store operation; and
writing the second partially merged store operation to a different write block of the cache line within the cache memory.

3. The method of claim 1 , wherein the method further includes based on determining that the second store operation does not specify the update to the byte adjacent to the byte to be updated by the first store operation, writing the first store operation into the cache memory.

4. The method of claim 1 , wherein the byte to be updated by the second store operation is located adjacent to a most significant bit of the byte to be updated by the first store operation.

5. The method of claim 1 , wherein the byte to be updated by the second store operation is located adjacent to a least significant bit of the byte to be updated by the first store operation.

6. The method of claim 1 , wherein writing store data of the fully merged store operation into a same write block of the cache line comprises writing the store data of the fully merged store operation into the write block is a single cycle of a processor core.

7. The method of claim 1 , wherein the cache memory includes only one write port.

8. A processing unit, comprising:
a cache memory having a plurality of cache lines; and
a load-store unit (LSU) configured to perform:
determining whether or not a second store operation specifies an update to a byte adjacent to a byte to be updated by a first store operation;
based on determining that the second store operation specifies the update to the byte adjacent to the byte to be updated by the first store operation, determining whether or not the total length of store data of the first and second store operations exceeds a maximum write block size of a cache line;
based on determining that the total length of the store data of the first and second store operations does not exceed the maximum write block size of the cache line, merging the first and second store operations to obtain a fully merged store operation and writing store data of the fully merged store operation into a same write block of the cache line; and
based on determining that the total length of the store data of the first and second store operations exceeds the maximum write block size of the cache line,
splitting the second store operation into first and second portions;
merging the first portion of the second store operation with the first store operation to obtain a first partially merged store operation; and
writing store data of the first partially merged store operation into the same write block of the cache line within the cache memory.

9. The processing unit of claim 8 , wherein the LSU further configured to perform
merging the second portion of the second store operation with a third store operation to obtain a second partially merged store operation; and
writing the second partially merged store operation to a different write block of the cache line within the cache memory.

10. The processing unit of claim 8 , wherein the LSU further configured to perform based on determining that the second store operation does not specify the update to the byte adjacent to the byte to be updated by the first store operation, writing the first store operation into the cache memory.

11. The processing unit of claim 8 , wherein the byte to be updated by the second store operation is located adjacent to a most or least significant bit of the byte to be updated by the first store operation.

12. The processing unit of claim 8 , wherein writing store data of the fully merged store operation into a same write block of the cache line comprises writing the store data of the fully merged store operation into the write block is a single cycle of the processing unit.

13. The processing unit of claim 8 , wherein the cache memory includes only one write port.

14. A data processing system, comprising:
a plurality of processing units in accordance with claim 8 ; and
an interconnect fabric coupling the plurality of processing units.

15. A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a processing unit, comprising:
a cache memory having a plurality of cache lines; and
a load-store unit (LSU) configured to perform:
determining whether or not a second store operation specifies an update to a byte adjacent to a byte to be updated by a first store operation;
based on determining that the second store operation specifies the update to the byte adjacent to the byte to be updated by the first store operation, determining whether or not the total length of store data of the first and second store operations exceeds a maximum write block size of a cache line;
based on determining that the total length of the store data of the first and second store operations does not exceed the maximum write block size of the cache line, merging the first and second store operations to obtain a fully merged store operation and writing store data of the fully merged store operation into a same write block of the cache line; and
based on determining that the total length of the store data of the first and second store operations exceeds the maximum write block size of the cache line,
splitting the second store operation into first and second portions;
merging the first portion of the second store operation with the first store operation to obtain a first partially merged store operation; and
writing store data of the first partially merged store operation into the same write block of the cache line within the cache memory.

16. The design structure of claim 15 , wherein the LSU further configured to perform
merging the second portion of the second store operation with a third store operation to obtain a second partially merged store operation; and
writing the second partially merged store operation to a different write block of the cache line within the cache memory.

17.

Assignees

• IBM

Inventors

• Cordes Robert A
• Lloyd Bryan

Classifications

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title