Execution elision of intermediate instruction by processor

Patent metadata

Field	Value
Publication number	US-11537402-B1
Application number	US-202117305734-A
Country	US
Kind code	B1
Filing date	Jul 14, 2021
Priority date	Jul 14, 2021
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A method for operation of a processor core is provided. First instruction data is consulted to determine whether a second instruction has execution data that matches the first instruction data. The first instruction data is from a first instruction. In response to determining that the second instruction has execution data that matches the first instruction data, prior data is copied into the second instruction. The first instruction depends on the prior data. After receiving an availability indication of the prior data, both the first instruction and the second instruction are woken for execution, without requiring execution of the first instruction before waking of the second instruction. The second instruction is executed by using the prior data as a skip of the first instruction. A computer system and a processor core configured to operate according to the method are also disclosed herein.

First claim

What is claimed is:

1. A method of operation of a processor core, the method comprising:
consulting first instruction data to determine whether a second instruction has execution data that matches the first instruction data, wherein the first instruction data is from a first instruction;
in response to determining that the second instruction has execution data that matches the first instruction data, copying, from the first instruction, a data location into the second instruction, wherein the first instruction depends on data that is to be stored at the data location;
after receiving an availability indication that the data is at the data location, issuing both the first instruction and the second instruction for execution, without requiring issuing of the first instruction before issuing the second instruction; and
executing the second instruction by using the data location to obtain the data and so as to skip the first instruction.

2. The method of claim 1 , wherein the consulting occurs in at least one member selected from a group consisting of a load-hit-store table and a bypass around a load-hit-store table.

3. The method of claim 1 , wherein the first instruction comprises a store instruction;
wherein the second instruction comprises a load instruction; and
wherein the store instruction is executed by storing the data in a memory address.

4. The method of claim 1 , wherein the data is generated from a prior instruction; and
wherein completion of the prior instruction generates the availability indication of the data that causes the first instruction and the second instruction to issue.

5. The method of claim 1 , wherein the executing the second instruction comprises:
retrieving data in a physical register file corresponding to the data location; and
sending the retrieved data to a mux via bypassing a store reorder queue.

6. The method of claim 1 , wherein the copying of the data location into the second instruction occurs into a field for dependency tracking.

7. The method of claim 1 , further comprising:
in further response to determining that the second instruction has execution data that matches the first instruction data, copying, from the first instruction, at least one member selected from the group consisting of an instruction tag and a data-availability written bit into the second instruction.

8. The method of claim 1 , wherein the first instruction is a store instruction; and
wherein the method further comprises writing an instruction tag of a producing instruction into a load-hit-store table, wherein the store instruction depends on the producing instruction.

9. The method of claim 8 , further comprising writing a first physical register file tag into the load-hit-store table, wherein the first physical register file tag represents a first register file location in a physical register file, and wherein execution of the producing instruction places data into the first register file location.

10. The method of claim 8 , wherein the second instruction is a load instruction;
wherein the instruction tag of the producing instruction is also copied from the second instruction into the first instruction; and
wherein the copying of the data location and the instruction tag into the second instruction comprises the load instruction reading out producing instruction information from the load-hit-store table.

11. The method of claim 10 , wherein the copying the data location into the second instruction comprises the load instruction reading out a first physical register file tag from the load-hit-store table, wherein the first physical register file tag represents a first register location in a physical register file, and wherein execution of the producing instruction places the data into the first register file location.

12. The method of claim 11 , wherein the executing the second instruction further comprises reading a value from the first register location.

13. The method of claim 12 , wherein the executing the second instruction further comprises loading the read value into a second register in the physical register file.

14. The method of claim 12 , further comprising forwarding the read value to a store forwarding mux and to a load result mux.

15. A computer system comprising one or more processors and one or more computer-readable memories, wherein a first processor of the one or more processors comprises a processor core configured to perform a method comprising:
consulting first instruction data to determine whether a second instruction has execution data that matches the first instruction data, wherein the first instruction data is from a first instruction;
in response to determining that the second instruction has execution data that matches the first instruction data, copying, from the first instruction, a data location into the second instruction, wherein the first instruction depends on data that is to be stored at the data location;
after receiving an availability indication that the data is at the data location, issuing both the first instruction and the second instruction for execution, without requiring issuing of the first instruction before issuing of the second instruction; and
executing the second instruction by using the data location to obtain the data and so as to skip the first instruction.

16. The computer system of claim 15 , wherein the first instruction comprises a store instruction;
wherein the second instruction comprises a load instruction; and
wherein the matching data relates to a memory address referred to by both the store instruction and the load instruction.

17. The computer system of claim 15 , wherein the first instruction is a store instruction; and
wherein the method further comprises writing an instruction tag of a producing instruction into a load-hit-store table, wherein the store instruction depends on the producing instruction.

18. A processor core comprising one or more hardware facilities comprising:
at least one execution unit for executing instructions comprising a first instruction, a second instruction, and a prior instruction; and
a physical register file;

wherein the processor core is capable of performing a method comprising:
consulting first instruction data to determine whether the second instruction has execution data that matches the first instruction data, wherein the first instruction data is from the first instruction;
in response to determining that the second instruction has execution data that matches the first instruction data, copying, from the first instruction, a data location into the second instruction, wherein the first instruction depends on data to be stored at the data location;
after receiving an availability indication that the data is at the data location, issuing both the first instruction and the second instruction for execution, without requiring issuing of the first instruction before issuing of the second instruction; and
executing the second instruction by using the data location to obtain the data and so as to skip the first instruction and by using the at least one execution unit;
wherein the executing the second instruction comprises using the physical register file.

19. The processor core of claim 18 , wherein the first instruction comprises a store instruction;
wherein the second instruction comprises a load instruction; and
wherein the store instruction is executed by storing the data in a memory address.

20. The processor core of claim 18 , wherein the first instruction i

Assignees

• IBM

Inventors

• Barrick Brian D
• Lloyd Bryan
• Nguyen Dung Q
• Thompto Brian W
• Gieske Edmund Joseph
• Griswell Jr John B

Classifications

• G06F9/30181

  Instruction operation extension or modification · CPC title

• G06F9/30141

  Implementation provisions of register files, e.g. ports · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3838 Primary

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/3834 Primary

  Maintaining memory consistency · CPC title