Prioritization of threads in a simultaneous multithreading processor core

Patent metadata

Field	Value
Publication number	US-11775337-B2
Application number	US-202117465228-A
Country	US
Kind code	B2
Filing date	Sep 2, 2021
Priority date	Sep 2, 2021
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

A first instruction for processing by a processor core is received. Whether the instruction is a larx is determined. Responsive to determining the instruction is a larx, whether a cacheline associated with the larx is locked is determined. Responsive to determining the cacheline associated with the larx is not locked, the cacheline associated with the larx is locked and a counter associated with a first thread of the processor core is started. The first thread is processing the first instruction.

First claim

The invention claimed is:

1. A computer-implemented method for prioritization of threads, the computer-implemented method comprising:
receiving, by one or more computer processors, a first instruction for processing by a processor core;
determining, by one or more computer processors, whether the first instruction is a larx;
responsive to determining the first instruction is the larx, determining, by one or more computer processors, whether a cacheline associated with the larx is locked; and
responsive to determining the cacheline associated with the larx is not locked, locking, by one or more computer processors, the cacheline associated with the larx and starting, by one or more computer processors, a counter associated with a first thread of the processor core, wherein the first thread is processing the first instruction;
wherein the counter associated with the first thread processing the first instruction increases by one for each cycle that an issue queue of the processor core is full.

2. The computer-implemented method of claim 1 , further comprising:
receiving, by one or more computer processors, a second instruction for processing by the processor core, wherein a second thread of the processor core is processing the second instruction;
determining, by one or more computer processors, an issue queue for processing the second instruction is full;
responsive to determining the issue queue is full, determining, by one or more computer processors, a value of the counter associated with the first thread.

3. The computer-implemented method of claim 2 , further comprising:
determining, by one or more computer processors, whether the value is greater than a threshold;
responsive to determining the value is greater than the threshold, flushing, by one or more computer processors, the issue queue of all instructions that are not being processed by the first thread.

4. The computer-implemented method of claim 3 , wherein the flushing is done by a dispatch hardware unit associated with the issue queue.

5. The computer-implemented method of claim 1 , wherein the larx instruction is selected from the group consisting of a lwarx, ldarx, lharx, and lbarx.

6. The computer-implemented method of claim 3 , wherein the threshold is 32.

7. A computer program product for prioritization of threads, the computer program product comprising:
one or more computer readable storage media; and
program instructions stored on the one or more computer readable storage media, the program instructions comprising:
program instructions to receive a first instruction for processing by a processor core;
program instructions to determine whether the first instruction is a larx;
responsive to determining the first instruction is the larx, program instructions to determine whether a cacheline associated with the larx is locked; and
responsive to determining the cacheline associated with the larx is not locked, program instructions to lock the cacheline associated with the larx and starting, by one or more computer processors, a counter associated with a first thread of the processor core, wherein the first thread is processing the first instruction;

wherein the counter associated with the first thread processing the first instruction increases by one for each cycle that an issue queue of the processor core is full.

8. The computer program product of claim 7 , further comprising program instructions stored on the one or more computer readable storage media, to:
receive a second instruction for processing by the processor core, wherein a second thread of the processor core is processing the second instruction;
determine an issue queue for processing the second instruction is full; and
responsive to determining the issue queue is full, determine a value of the counter associated with the first thread.

9. The computer program product of claim 8 , further comprising program instructions stored on the one or more computer readable storage media, to:
determine whether the value is greater than a threshold; and
responsive to determining the value is greater than the threshold, flush the issue queue of all instructions that are not being processed by the first thread.

10. The computer program product of claim 9 , wherein the flushing is done by a dispatch hardware unit associated with the issue queue.

11. The computer program product of claim 7 , wherein the larx instruction is selected from the group consisting of a lwarx, ldarx, lharx, and lbarx.

12. The computer program product of claim 9 , wherein the threshold is 32.

13. A computer system for prioritization of threads, the computer system comprising:
one or more computer processors;
one or more computer readable storage media; and
program instructions, stored on the one or more computer readable storage media for execution by at least one of the one or more computer processors, the program instructions comprising:
program instructions to receive a first instruction for processing by a processor core;
program instructions to determine whether the first instruction is a larx;
responsive to determining the first instruction is the larx, program instructions to determine whether a cacheline associated with the larx is locked; and
responsive to determining the cacheline associated with the larx is not locked, program instructions to lock the cacheline associated with the larx and starting, by one or more computer processors, a counter associated with a first thread of the processor core, wherein the first thread is processing the first instruction;

wherein the counter associated with the first thread processing the first instruction increases by one for each cycle that an issue queue of the processor core is full.

14. The computer system of claim 13 , further comprising program instructions stored on the one or more computer readable storage media for execution by at least one of the one or more computer processors, to:
receive a second instruction for processing by the processor core, wherein a second thread of the processor core is processing the second instruction;
determine an issue queue for processing the second instruction is full; and
responsive to determining the issue queue is full, determine a value of the counter associated with the first thread.

15. The computer system of claim 14 , further comprising program instructions stored on the one or more computer readable storage media for execution by at least one of the one or more computer processors, to:
determine whether the value is greater than a threshold; and
responsive to determining the value is greater than the threshold, flush the issue queue of all instructions that are not being processed by the first thread.

16. The computer system of claim 15 , wherein the flushing is done by a dispatch hardware unit associated with the issue queue.

17. The computer system of claim 13 , wherein the larx instruction is selected from the group consisting of a lwarx, ldarx, lharx, and lbarx.

Assignees

• IBM

Inventors

• Lloyd Bryan
• Guthrie Guy L
• Eisen Susan E
• Jeganathan Dhivya
• Murray Luke

Classifications

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/4818 Primary

  Priority circuits therefor · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30087

  Synchronisation or serialisation instructions · CPC title

• G06F9/526 Primary

  Mutual exclusion algorithms · CPC title