Gather buffer management for unaligned and gather load operations

Patent metadata

Field	Value
Publication number	US-11755324-B2
Application number	US-202117462620-A
Country	US
Kind code	B2
Filing date	Aug 31, 2021
Priority date	Aug 31, 2021
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

A computer system, processor, programming instructions and/or method for managing operations of a gather buffer for a processor core load storage unit. The processor core includes a processing pipeline having one or more execution units for processing unaligned load instructions that executes in two phases to satisfy. A buffer storage element is provided having a plurality of entries for temporarily collecting partial writeback results retrieved from the memory that are associated with first phase accesses for each of a plurality of unaligned load instructions. An associated logic controller device tracks two parts of the unaligned load to be gathered at independent times, wherein said partial result stored at said buffer storage element comprises a first part of an unaligned load. The second phase load access for the same instruction is independently accessed and later merged with first part of the load data at byte granularity to satisfy the load.

First claim

The invention claimed is:

1. A system for processing information in a processor, the system comprising:
a processing pipeline having one or more execution units for processing unaligned load instructions;
a memory for storing data, said data retrieved from the memory by an execution unit when processing an unaligned load instruction;
a gather buffer temporarily storing partial writeback data results retrieved from the memory, a partial writeback data result comprising a first part of an unaligned load data received from the memory when processing the unaligned load instruction; and
a gather buffer controller associated with said gather buffer, said gather buffer controller tracking the first part of the unaligned load data and tracking a second part of the unaligned load data to be collected at an arbitrary later time, said gather buffer controller comprising a plurality of entries, each respective entry storing a respective identifier tag associated with an address of an unaligned load data for identifying a respective unaligned load instruction, wherein the first part of the unaligned load data is retrieved from said gather buffer for merging with said second part of the unaligned load data to satisfy the unaligned load instruction.

2. The system as claimed in claim 1 , wherein said gather buffer comprises a plurality of entries in one-to-one correspondence with said plurality of entries of said gather buffer controller, said gather buffer controller controlling writing of said partial writeback data results to and reading of said partial writeback data results from an entry of said gather buffer at byte granularity.

3. The system as claimed in claim 2 , wherein said gather buffer controller comprises:
a circuit for comparing an identifier tag associated with the second part of said unaligned load data to be collected with an identifier tag associated with each partial writeback data result, the identifier tag associated with each partial writeback data result being prior stored at entries of said gather buffer controller; and in response to finding a matching identifier tag at an entry, asserting a signal to read the stored partial writeback data result from a corresponding gather buffer entry for merging with the second part of said unaligned load data.

4. The system as claimed in claim 3 , further comprising:
a merging circuit for merging the first part of the unaligned load data stored at said gather buffer with the second part of the unaligned load data to be collected.

5. The system as claimed in claim 4 , wherein said merging circuit comprises a logic OR device, said logic OR device aligning the stored first part of the unaligned load data output from a gather buffer entry with the second part of that unaligned load data, wherein all unaligned load data is returned via a data bus for use by said processor.

6. The system as claimed in claim 4 , further comprising:
a data bus used to conduct the first part of said unaligned load data and the second part of said unaligned load data to said gather buffer; and
a formatter for byte aligning partial results with the data bus as if both first part and second part of all the data were retrieved.

7. The system as claimed in claim 3 , further comprising:
a logic queue for storing unprocessed unaligned load instructions to be launched for data retrieval.

8. The system as claimed in claim 7 , further comprising:
a logic circuit for detecting a load operation instruction having a load unaligned to a memory boundary and upon detecting an unaligned load, generating one of: a first unaligned load signal to said gather buffer controller indicating a first part of said unaligned load instruction to be processed or a second unaligned load signal to said gather buffer controller indicating a second part of said unaligned load instruction to be processed.

9. The system as claimed in claim 8 , wherein said gather buffer controller further comprises:
a detecting circuit for detecting available entries in said gather buffer controller and corresponding entries in said gather buffer in response to said first unaligned load signal, said detecting circuit asserting a buffer full signal when no available entries are available for storing partial writeback data results at said gather buffer,
said logic queue responsive to said buffer full signal for storing unprocessed unaligned load instructions.

10. The system as claimed in claim 9 , wherein said detecting circuit of said gather buffer controller asserts a wakeup signal to said logic queue in response to detecting an available entry in said gather buffer for storing partial writeback data results,
said logic queue responsive to said wakeup signal for launching an unprocessed unaligned load instruction.

11. The system as claimed in claim 10 , wherein said gather buffer controller asserts a completion signal to said logic queue indicating a completion of said storing said partial writeback data results retrieved from the memory,
said logic queue responsive to said completion signal for re-launching said unaligned load instruction.

12. A method for processing information in a processor, the method comprising:
providing a processing pipeline having one or more execution units for processing unaligned load instructions, said processor having an associated memory for storing data, said data retrieved from the memory by one of the one or more execution units when processing an unaligned load instruction;
temporarily storing, at a gather buffer associated with an execution unit, partial writeback data results retrieved from the memory, a partial writeback data result comprising a first part of an unaligned load data received from the memory when processing the unaligned load instruction; and
tracking, at a gather buffer controller associated with said gather buffer, the first part of the unaligned load data and tracking a second part of the unaligned load data to be collected at an arbitrary later time, said gather buffer controller comprising a plurality of entries, each respective entry storing a respective identifier tag associated with an address of an unaligned load data for identifying a respective unaligned load instruction, wherein the first part of the unaligned load data is retrieved from said gather buffer for merging with said second part of the unaligned load data to satisfy the unaligned load instruction.

13. The method as claimed in claim 12 , wherein
said gather buffer comprises a plurality of entries in one-to-one correspondence with said plurality of entries of said gather buffer controller, said method comprising:
controlling, by said gather buffer controller, a writing of writeback data results to and reading of said writeback data results from an entry of said gather buffer at byte granularity.

14. The method as claimed in claim 13 , further comprising:
comparing an identifier tag associated with the second part of said unaligned load data to be collected with an identifier tag associated with each partial writeback data result, the identifier tag associated with each partial writeback data result being prior stored at entries of said gather buffer controller; and
in response to finding a matching identifier tag at an entry, asserting a signal to read the stored partial writeback data result from a corresponding gather buffer entry for merging with the second part of said unaligned load data.

15. The method as claimed in claim 12 , further comprising:
merging the first part of an unaligned load data stored at said gather buffer with the second part of the unaligned load data to be collected, said me

Assignees

• IBM

Inventors

• Fernsler Kimberly M
• Lloyd Bryan
• Hrusecky David A
• Campbell David A

Classifications

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3858

  Result writeback, i.e. updating the architectural state or memory · CPC title

• G06F9/30043 Primary

  LOAD or STORE instructions; Clear instruction · CPC title