Area and power efficient mechanism to wakeup store-dependent loads according to store drain merges

Patent metadata

Field	Value
Publication number	US-11243773-B1
Application number	US-202017120371-A
Country	US
Kind code	B1
Filing date	Dec 14, 2020
Priority date	Dec 14, 2020
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

A computer system, includes a store queue that holds store entries and a load queue that holds load entries sleeping on a store entry. A processor detects a store drain merge operation call and generates a pair of store tags comprising a first store tag corresponding to a first store entry to be drained and a second store tag corresponding to a second store entry to be drained. The processor determines the pair of store tags an even-type store tag or an odd-type store tag. The processor disables the odd store tag included in the even-type store tag pair when detecting the even-type store tag pair, and wakes up a first load entry dependent on the even store tag and a second load entry dependent on the odd store tag based on the even store tag included in the even-type store tag pair while the odd store tag is disabled.

First claim

What is claimed is:

1. A computer-implemented method for executing a store drain merge operation to wakeup load entries sleeping on dependent store entries, the method comprising:
detecting, by a processor, a call to perform the store drain merge operation;
generating a pair of store tags comprising a first store tag corresponding to a first store entry to be drained and a second store tag corresponding to a second store entry to be drained;
determining the pair of store tags is one of an even-type store tag and an odd-type store tag, the even-type store tag pair including the first store tag as an even store tag and the second store tag as an odd store tag, and the odd-type store tag including the first store tag as an odd store tag and the second store tag as an even store tag;
in response to determining the even-type store tag pair, disabling the odd store tag included in the even-type store tag pair; and
waking up a first load entry dependent on the even store tag and a second load entry dependent on the odd store tag based on the even store tag included in the even-type store tag pair while the odd store tag is disabled.

2. The computer-implemented method of claim 1 , wherein the first and second load entries are woken in a single given clock cycle of the processor.

3. The computer-implemented method of claim 1 , wherein the even and odd store tags are defined as a plurality of bits.

4. The computer-implemented method of claim 3 , wherein disabling the odd store tag includes disabling the least significant bit (LSB) of the odd store tag.

5. The computer-implemented method of claim 3 , wherein in response to determining the odd-type store tag pair, waking up a first load entry dependent on the odd store tag during a first clock cycle of the processor and delaying wakeup of a second load entry dependent on the even store tag until a subsequent clock cycle following the first clock cycle.

6. The computer-implemented method of claim 5 , wherein delaying the wakeup of the second load entry includes disabling the LSB of the even store tag.

7. The computer-implemented method of claim 6 , delaying the wakeup of the second load entry until the subsequent clock cycle excludes a call to perform the store drain merge operation.

8. A computer system, comprising:
a store queue unit configured to hold at least one store entry to be completed;
a load queue unit configured to hold at least one load entry sleeping on a store entry included in the store queue unit;
a processor configured to detect a call to perform a store drain merge operation and to generate a pair of store tags comprising a first store tag corresponding to a first store entry to be drained from the store queue unit and a second store tag corresponding to a second store entry to be drained from the store queue unit,
wherein the processor determines the pair of store tags is one of an even-type store tag and an odd-type store tag, the even-type store tag pair including the first store tag as an even store tag and the second store tag as an odd store tag, and the odd-type store tag including the first store tag as an odd store tag and the second store tag as an even store tag, disables the odd store tag included in the even-type store tag pair in response to determining the even-type store tag pair, and wakes up a first load entry dependent on the even store tag and a second load entry dependent on the odd store tag based on the even store tag included in the even-type store tag pair while the odd store tag is disabled.

9. The computer system of claim 8 , wherein the first and second load entries are woken in a single given clock cycle of the processor.

10. The computer system of claim 8 , wherein the even and odd store tags are defined as a plurality of bits.

11. The computer system of claim 10 , wherein disabling the odd store tag includes disabling the least significant bit (LSB) of the odd store tag.

12. The computer system of claim 10 , wherein in response to determining the odd-type store tag pair, waking up a first load entry dependent on the odd store tag during a first clock cycle of the processor and delaying wakeup of a second load entry dependent on the even store tag until a subsequent clock cycle following the first clock cycle.

13. The computer system of claim 12 , wherein delaying the wakeup of the second load entry includes disabling the LSB of the even store tag.

14. The load entry of claim 13 , delaying the wakeup of the second load entry until the subsequent clock cycle excludes a call to perform the store drain merge operation.

15. A computer program product to control a computer system to execute a store drain merge operation to wakeup load entries sleeping on dependent store entries, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by an electronic computer processor to control the processor to perform operations comprising:
detecting, by the processor, a call to perform the store drain merge operation;
generating a pair of store tags comprising a first store tag corresponding to a first store entry to be drained and a second store tag corresponding to a second store entry to be drained;
determining the pair of store tags is one of an even-type store tag and an odd-type store tag, the even-type store tag pair including the first store tag as an even store tag and the second store tag as an odd store tag, and the odd-type store tag including the first store tag as an odd store tag and the second store tag as an even store tag;
in response to determining the even-type store tag pair, disabling the odd store tag included in the even-type store tag pair; and
waking up a first load entry dependent on the even store tag and a second load entry dependent on the odd store tag based on the even store tag included in the even-type store tag pair while the odd store tag is disabled.

16. The computer program product of claim 15 , wherein the first and second load entries are woken in a single given clock cycle of the processor.

17. The computer program product of claim 15 , wherein the even and odd store tags are defined as a plurality of bits.

18. The computer program product of claim 17 , wherein disabling the odd store tag includes disabling the least significant bit (LSB) of the odd store tag.

19. The computer program product of claim 17 , wherein in response to determining the odd-type store tag pair, waking up a first load entry dependent on the odd store tag during a first clock cycle of the processor and delaying wakeup of a second load entry dependent on the even store tag until a subsequent clock cycle following the first clock cycle.

20. The computer program product of claim 19 , wherein delaying the wakeup of the second load entry includes disabling the LSB of the even store tag until the subsequent clock cycle excludes a call to perform the store drain merge operation.

Assignees

• IBM

Inventors

• Lloyd Bryan
• Campbell David
• Chen Brian
• Cordes Robert A

Classifications

• G06F9/3838 Primary

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F9/30047

  Prefetch instructions; cache control instructions · CPC title

• G06F9/3842

  Speculative instruction execution · CPC title

• G06F9/384

  Register renaming · CPC title