Processor overriding of a false load-hit-store detection

Patent metadata

Field	Value
Publication number	US-11687337-B2
Application number	US-202117445541-A
Country	US
Kind code	B2
Filing date	Aug 20, 2021
Priority date	Aug 20, 2021
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

A method for operation of a processor core is provided. A rejected first load instruction is received that has been rejected due to a false load-hit-store detection against a first store instruction. A warning label is generated on a basis of the false load-hit-store detection. The warning label is added to the received first load instruction to create a labeled first load instruction. The labeled first load instruction is issued such that the warning label causes the labeled first load instruction to bypass the first store instruction in the store reorder queue and thereby avoid another false load-hit-store detection against the first store instruction. A computer system and a processor core configured to operate according to the method are also disclosed herein.

First claim

What is claimed is:

1. A method of operation of a processor core, the method comprising:
receiving a rejected first load instruction, wherein the rejected first load instruction has been rejected due to a false load-hit-store detection against a first store instruction;
generating a warning label in response to receiving the false load-hit-store detection;
adding the warning label to the received first load instruction to create a labeled first load instruction; and
issuing the labeled first load instruction such that the warning label causes the labeled first load instruction to bypass the first store instruction in a store reorder queue and thereby avoid another false load-hit-store detection against the first store instruction.

2. The method of claim 1 , wherein the warning label comprises an identifier of the first store instruction.

3. The method of claim 1 , wherein the false load-hit-store detection occurs due to a partial address of the first load instruction matching a partial address of the first store instruction and a full address of the first load instruction not matching a full address of the first store instruction.

4. The method of claim 1 , wherein the issuing of the labeled first load instruction occurs before the first store instruction drains from the store reorder queue.

5. The method of claim 1 , wherein the issuing of the labeled first load instruction occurs from a main core issue queue.

6. The method of claim 1 , wherein the issuing of the labeled first load instruction occurs from a load instruction issue queue local to a load store unit.

7. The method of claim 1 , further comprising executing the issued labeled first load instruction.

8. The method of claim 1 , wherein the warning label implements instruction age misinterpretation to cause the labeled first load instruction to bypass the first store instruction in the store reorder queue.

9. The method of claim 1 , further comprising receiving the issued labeled first load instruction after the issued labeled first load instruction is further rejected due to a false load-hit-store detection against a second store instruction;
generating a further warning label on a basis of the second store instruction;
adding the further warning label to the labeled first load instruction so that a further labeled first load instruction is created; and
issuing the further labeled first load instruction such that the further warning label causes the issued further labeled first load instruction to bypass the second store instruction in the store reorder queue and thereby avoid another false load-hit-store detection against the second store instruction.

10. The method of claim 9 , wherein the second store instruction is a next older instruction than the first store instruction in a program sequence.

11. The method of claim 9 , wherein the further warning label comprises an identifier of the second store instruction.

12. The method of claim 9 , further comprising executing the issued further labeled first load instruction.

13. The method of claim 9 , wherein the further warning implements instruction age misinterpretation to cause the issued further labeled first load instruction to bypass the second store instruction in the store reorder queue.

14. A computer system comprising one or more processors and one or more computer-readable memories, wherein a first processor of the one or more processors comprises a processor core configured to perform a method comprising:
receiving a rejected first load instruction, wherein the rejected first load instruction has been rejected due to a false load-hit-store detection against a first store instruction;
generating a warning label in response to receiving the false load-hit-store detection;
adding the warning label to the received first load instruction to create a labeled first load instruction; and
issuing the labeled first load instruction such that the warning label causes the labeled first load instruction to bypass the first store instruction in a store reorder queue and thereby avoid another false load-hit-store detection against the first store instruction.

15. The computer system of claim 14 , wherein the warning label comprises an identifier of the first store instruction.

16. The computer system of claim 14 , wherein the false load-hit-store detection occurs due to a partial address of the first load instruction matching a partial address of the first store instruction and a full address of the first load instruction not matching a full address of the first store instruction.

17. The computer system of claim 14 , wherein the warning label implements instruction age misinterpretation to cause the labeled first load instruction to bypass the first store instruction in the store reorder queue.

18. A processor core comprising one or more hardware facilities comprising at least one execution unit for executing instructions, wherein the processor core is capable of performing a method comprising:
receiving a rejected first load instruction, wherein the rejected first load instruction has been rejected due to a false load-hit-store detection against a first store instruction;
generating a warning label in response to receiving the false load-hit-store detection;
adding the warning label to the received first load instruction to create a labeled first load instruction; and
issuing the labeled first load instruction such that the warning label causes the labeled first load instruction to bypass the first store instruction in a store reorder queue and thereby avoid another false load-hit-store detection against the first store instruction.

19. The processor core of claim 18 , wherein the warning label comprises an identifier of the first store instruction.

20. The processor core of claim 18 , wherein the warning label implements instruction age misinterpretation to cause the labeled first load instruction to bypass the first store instruction in the store reorder queue.

Assignees

• IBM

Inventors

• Lloyd Bryan
• Chen Brian
• Fernsler Kimberly M

Classifications

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/30043 Primary

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3834 Primary

  Maintaining memory consistency · CPC title

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title