Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operations

Patent metadata

Field	Value
Publication number	US-11263151-B2
Application number	US-202016941630-A
Country	US
Kind code	B2
Filing date	Jul 29, 2020
Priority date	Jul 29, 2020
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

Translation lookaside buffer (TLB) invalidation using virtual addresses is provided. A cache is searched for a virtual address matching the input virtual address. Based on a matching virtual address in the cache, the corresponding cache entry is invalidated. The load/store queue is searched for a set and a way corresponding to the set and the way of the invalidated cache entry. Based on an entry in the load/store queue matching the set and the way of the invalidated cache entry, the entry in the load/store queue is marked as pending. Indicating a completion of the TLB invalidate instruction is delayed until all pending entries in the load/store queues are complete.

First claim

What is claimed is:

1. A method for translation lookaside buffer (TLB) invalidation, comprising:
receiving a TLB invalidate instruction at a core of a plurality cores, wherein the TLB invalidate instruction includes an input virtual address to be invalidated;
searching in a cache for a virtual address matching the input virtual address;
based on a matching virtual address in the cache, invalidating the corresponding cache entry;
searching a load/store queue for a set and a way corresponding to the set and the way of the invalidated cache entry;
based on an entry in the load/store queue matching the set and the way of the invalidated cache entry, marking the entry in the load/store queue as pending; and
delaying indicating a completion of the TLB invalidate instruction until all pending entries in the load/store queues are complete.

2. The method of claim 1 , wherein:
the set is an index into the cache and the way is an associativity.

3. The method of claim 1 , wherein only the set is used when marking as pending the load/store queue entry of an evicted cache entry.

4. The method of claim 1 , wherein a combined the set and the way in the load/store queue entry is a pointer to the cache line.

5. The method of claim 1 , wherein the set is derived from a subset of an effective address.

6. The method of claim 1 , further comprising:
reloading a cache line in response to the cache line being previously evicted, wherein the reloading comprises allocating a new set and a new way;
searching the load/store queue for an entry having a set and a way corresponding to the new set and the new way; and
indicating in the load/store queue entry that the cache line in the load/store queue entry is evicted.

7. The method of claim 6 , further comprising:
marking the entry in the load/store queue as pending based on the entry in the load/store queue being evicted and having the set matching the new set.

8. A computer program product for translation lookaside buffer (TLB) invalidation, wherein the computer program product comprises a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processing unit to cause the processing unit to perform a method comprising:
receiving a TLB invalidate instruction at a core of a plurality cores, wherein the TLB invalidate instruction includes an input virtual address to be invalidated;
searching in a cache for a virtual address matching the input virtual address;
based on a matching virtual address in the cache, invalidating the corresponding cache entry;
searching a load/store queue for a set and a way corresponding to the set and the way of the invalidated cache entry;
based on an entry in the load/store queue matching the set and the way of the invalidated cache entry, marking the entry in the load/store queue as pending; and
delaying indicating a completion of the TLB invalidate instruction until all pending entries in the load/store queues are complete.

9. The computer program product of claim 8 , wherein:
the set is an index into the cache and the way is an associativity.

10. The computer program product of claim 8 , wherein only the set is used when marking as pending the load/store queue entry of an evicted cache entry.

11. The computer program product of claim 8 , wherein a combined the set and the way in the load/store queue entry is a pointer to the cache line.

12. The computer program product of claim 8 , wherein the set is derived from a subset of an effective address.

13. The computer program product of claim 8 , further comprising:
reloading a cache line in response to the cache line being previously evicted, wherein the reloading comprises allocating a new set and a new way;
searching the load/store queue for an entry having a set and a way corresponding to the new set and the new way; and
indicating in the load/store queue entry that the cache line in the load/store queue entry is evicted.

14. The computer program product of claim 13 , further comprising:
marking the entry in the load/store queue as pending based on the entry in the load/store queue being evicted and having the set matching the new set.

15. A computer system for translation lookaside buffer (TLB) invalidation, comprising:
one or more processors; and a computer-readable memory coupled to the one or more processors, the computer-readable memory comprising instructions for:
searching in a cache for a virtual address matching the input virtual address;
based on a matching virtual address in the cache, invalidating the corresponding cache entry;
searching a load/store queue for a set and a way corresponding to the set and the way of the invalidated cache entry;
based on an entry in the load/store queue matching the set and the way of the invalidated cache entry, marking the entry in the load/store queue as pending; and
delaying indicating a completion of the TLB invalidate instruction until all pending entries in the load/store queues are complete.

16. The computer system of claim 15 , wherein:
the set is an index into the cache and the way is an associativity.

17. The computer system of claim 15 , wherein only the set is used when marking as pending the load/store queue entry of an evicted cache entry.

18. The computer system of claim 15 , wherein a combined the set and the way in the load/store queue entry is a pointer to the cache line, and wherein the set is derived from a subset of an effective address.

19. The computer system of claim 15 , further comprising:
reloading a cache line in response to the cache line being previously evicted, wherein the reloading comprises allocating a new set and a new way;
searching the load/store queue for an entry having a set and a way corresponding to the new set and the new way; and
indicating in the load/store queue entry that the cache line in the load/store queue entry is evicted.

20. The computer system of claim 19 , further comprising:
marking the entry in the load/store queue as pending based on the entry in the load/store queue being evicted and having the set matching the new set.

Assignees

• IBM

Inventors

• Campbell David
• Lloyd Bryan
• Hrusecky David A
• Fernsler Kimberly M
• Stuecheli Jeffrey A
• Guthrie Guy L
• Kirchhoff Samuel David
• Cordes Robert A
• Mack Michael J
• Chen Brian

Classifications

• G06F2212/683

  Invalidation · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F9/3834 Primary

  Maintaining memory consistency · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F9/546

  Message passing systems or structures, e.g. queues · CPC title