Carbon replenishment of silicon-containing materials to reduce thickness loss
US-2025112054-A1 · Apr 3, 2025 · US
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Labonte Andre P patents
Labonte Andre P is listed as an inventor on 45 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Labonte Andre P |
| Total patents | 45 |
| First publication | Oct 29, 2015 |
| Latest publication | Apr 3, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Method for manufacturing optical device structures
US-12158605-B2 · Dec 3, 2024 · US
Method for manufacturing optical device structures
US-2024295688-A1 · Sep 5, 2024 · US
Uniform sige channel in nanosheet architecture
US-2024274724-A1 · Aug 15, 2024 · US
Method for manufacturing optical device structures
US-12013566-B2 · Jun 18, 2024 · US
Method for manufacturing optical device structures
US-2023021915-A1 · Jan 26, 2023 · US
Method for manufacturing optical device structures
US-11487058-B2 · Nov 1, 2022 · US
Interconnect structures of semiconductor devices having a via structure through an upper conductive line
US-11380581-B2 · Jul 5, 2022 · US
Method for manufacturing optical device structures
US-2022050241-A1 · Feb 17, 2022 · US
Methods of forming variable-depth device structures
US-11112694-B2 · Sep 7, 2021 · US
Recent patents
Latest publications not already listed above.
Gate tie-down enablement with inner spacer
US-10879375-B2 · Dec 29, 2020 · US
Methods of forming variable-depth device structures
US-2020363719-A1 · Nov 19, 2020 · US
Sacrificial gate spacer regions for gate contacts formed over the active region of a transistor
US-10832961-B1 · Nov 10, 2020 · US
Interconnect structure having reduced resistance variation and method of forming same
US-10832944-B2 · Nov 10, 2020 · US
Sacrificial gate spacer regions for gate contacts formed over the active region of a transistor
US-2020335401-A1 · Oct 22, 2020 · US
Contact structures
US-10790376-B2 · Sep 29, 2020 · US
Interconnect structures of semiconductor devices
US-2020152512-A1 · May 14, 2020 · US
Interconnect structure having reduced resistance variation and method of forming same
US-2020144106-A1 · May 7, 2020 · US
Contact structures
US-2020058757-A1 · Feb 20, 2020 · US
Gate tie-down enablement with inner spacer
US-10522654-B2 · Dec 31, 2019 · US
Gate tie-down enablement with inner spacer
US-2019363178-A1 · Nov 28, 2019 · US
Local interconnect structure including non-eroded contact via trenches
US-10388602-B2 · Aug 20, 2019 · US
Gate tie-down enablement with inner spacer
US-10332977-B2 · Jun 25, 2019 · US
Methods of forming a semiconductor device with a gate contact positioned above the active region
US-10204994-B2 · Feb 12, 2019 · US
Gate tie-down enablement with inner spacer
US-2018374932-A1 · Dec 27, 2018 · US
Gate tie-down enablement with inner spacer
US-10128352-B2 · Nov 13, 2018 · US
Methods of forming a semiconductor device with a gate contact positioned above the active region
US-2018286956-A1 · Oct 4, 2018 · US
Gate tie-down enablement with inner spacer
US-2018151433-A1 · May 31, 2018 · US
Methods of forming a gate contact for a transistor above an active region and the resulting device
US-9947589-B1 · Apr 17, 2018 · US
Gate tie-down enablement with inner spacer
US-9941163-B2 · Apr 10, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Globalfoundries Inc | 37 |
| IBM | 24 |
| Applied Materials Inc | 10 |
| Globalfoundries Us Inc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W20/069 | 35 |
| H10W20/0698 | 29 |
| H10W20/076 | 25 |
| H10D64/017 | 24 |
| H10P50/283 | 24 |