Gate tie-down enablement with inner spacer

Patent metadata

Field	Value
Publication number	US-10332977-B2
Application number	US-201815880059-A
Country	US
Kind code	B2
Filing date	Jan 25, 2018
Priority date	Aug 10, 2015
Publication date	Jun 25, 2019
Grant date	Jun 25, 2019

Abstract

A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

First claim

The invention claimed is:

1. A method for forming a gate tie-down, comprising:
concurrently forming trench contacts on opposing sides of a gate structure and exposing a gate conductor in the gate structure; and
forming a conductive material in an opening through an interlevel dielectric (ILD) to provide a self-aligned contact down to the trench contact on one side of the gate structure and to form a gate contact down to the gate conductor and a horizontal connection within the ILD between the gate conductor and the self-aligned contact.

2. The method as recited in claim 1 , wherein gate spacers and inner spacers permit contact between the self-aligned contact and the gate contact and prevent contact between the trench contact on one side of the gate structure and the gate conductor.

3. The method as recited in claim 1 , wherein the forming the conductive material further includes forming the ILD on the gate conductor and the trench contacts and over other gate structures.

4. The method as recited in claim 3 , wherein the forming the conductive material further includes opening up the ILD to expose the trench contact on the one side of the gate structure and the gate conductor.

5. The method as recited in claim 4 , wherein opening up the ILD includes performing a lithography, etch, lithography, etch (LELE) procedure wherein one lithography and etch forms a contact hole for the self-aligned contact and the other lithography and etch forms a contact hole for the gate contact.

6. The method as recited in claim 4 , wherein opening up the ILD includes performing a lithography, freeze, lithography, etch (LFLE) procedure wherein one lithography forms a contact hole pattern for the self-aligned contact, which is frozen, and the other lithography forms a contact hole pattern for the gate contact before etching.

7. The method as recited in claim 4 , wherein opening up the ILD includes performing an extreme ultraviolet (EUV) lithography using a same color lithography to form patterns for the gate contact and the self-aligned contact before etching.

8. The method as recited in claim 1 , wherein the gate contact is self-aligned to the trench contact on one side of the gate structure.

9. The method as recited in claim 1 , further comprising opening up a cap layer to expose the gate conductor.

10. The method as recited in claim 9 , wherein the ILD includes a thickness above the cap layer of gate structures and the horizontal connection is formed within the thickness of the ILD.

11. A method for forming a gate tie-down, comprising:
recessing gate spacers on a gate structure to expose a gate conductor;
exposing trench contacts on opposing sides of the gate structure; and
forming a conductive material in an opening through an interlevel dielectric (ILD) to form a self-aligned contact down to one trench contact on one side of the gate structure and to form a gate contact down to the gate conductor to form a gate tie-down between the one trench contact and the gate conductor.

12. The method as recited in claim 11 , wherein the gate spacers and inner spacers formed on the gate spacers permit contact between the self-aligned contact and the gate contact and prevent contact between the trench contact and the gate conductor.

13. The method as recited in claim 11 , wherein the forming the conductive material further includes depositing the ILD on the gate conductor and over the gate structure.

14. The method as recited in claim 13 , wherein the forming the conductive material further includes opening the ILD to expose the trench contact on the one side of the gate structure and the gate conductor.

15. The method as recited in claim 14 , wherein opening up the ILD includes performing a lithography, etch, lithography, etch (LELE) procedure wherein one lithography and etch forms a contact hole for the self-aligned contact and the other lithography and etch forms a contact hole for the gate contact.

16. The method as recited in claim 14 , wherein opening up the ILD includes performing a lithography, freeze, lithography, etch (LFLE) procedure wherein one lithography forms a contact hole pattern for the self-aligned contact, which is frozen, and the other lithography forms a contact hole pattern for the gate contact before etching.

17. The method as recited in claim 14 , wherein opening up the ILD includes performing an extreme ultraviolet (EUV) lithography using a same color lithography to form patterns for the gate contact and the self-aligned contact before etching.

18. The method as recited in claim 14 , wherein the gate contact is self-aligned to the trench contact.

19. The method as recited in claim 11 , further comprising opening up a cap layer to expose the gate conductor.

20. The method as recited in claim 19 , wherein the ILD includes a thickness above the cap layer of the gate structure and the horizontal connection is formed within the thickness of the ILD.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Fan Su Chen
• Labonte Andre P
• Liebmann Lars W
• Mehta Sanjay C

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title