Interconnect structures of semiconductor devices having a via structure through an upper conductive line

Patent metadata

Field	Value
Publication number	US-11380581-B2
Application number	US-201816185015-A
Country	US
Kind code	B2
Filing date	Nov 9, 2018
Priority date	Nov 9, 2018
Publication date	Jul 5, 2022
Grant date	Jul 5, 2022

Abstract

A method of fabricating an interconnect structure of a semiconductor device is provided having a first conductive line and forming a second conductive line over the first conductive line. A via opening is formed in the second conductive line, and the via opening is aligned over the first conductive line. The via opening is filled with a conductive material to form an interconnect via and an upper portion of the interconnect via forms a portion of the second conductive line.

First claim

What is claimed is:

1. A method of fabricating an interconnect structure of a semiconductor device, the method comprising:
forming a first dielectric layer over a first conductive line;
forming a second conductive line over the first dielectric layer;
forming a second dielectric layer over the first dielectric layer and adjacent to the second conductive line;
forming a via opening through the second conductive line, wherein the via opening is aligned over the first conductive line and has a width equal to a width of the second conductive line;
removing a portion of the first dielectric layer beneath the via opening to extend the via opening to an upper surface of the first conductive line before filling the via opening with a conductive material to form an interconnect via, wherein extending of the via opening to the upper surface of the first conductive line comprises an etching process, wherein the first dielectric layer and the second dielectric layer are etched by the etching process, wherein the second dielectric layer etches slower than the first dielectric layer during the etching process; and
filling the via opening with the conductive material to form the interconnect via, wherein an upper portion of the interconnect via forms a portion of the second conductive line.

2. The method of claim 1 , wherein removing the portion of the first dielectric layer, further comprises:
removing additional portions of the first dielectric layer from areas on both sides of the first conductive line to a level less than 10 nm below the upper surface of the first conductive line.

3. The method of claim 1 , wherein forming the interconnect via, further comprises:
recessing the first conductive line;
depositing an etch stop layer between the recessed first conductive line and the first dielectric layer;
removing a portion of the first dielectric layer beneath the via opening to expose a portion of the etch stop layer; and
removing the exposed portion of the etch stop layer to expose the first conductive line before filling the via opening with the conductive material to form the interconnect via.

4. The method of claim 1 wherein the interconnect via and the second conductive line are formed of different conductive materials.

5. The method of claim 1 wherein the interconnect via and the second conductive line are formed of the same conductive material.

6. The method of claim 1 wherein the second conductive line comprises a conductive material that can be etched by a plasma etching process.

7. The method of claim 1 wherein the second conductive line comprises Ru or Co.

8. The method of claim 1 wherein the interconnect via has a width at least as wide as the first conductive line.

9. The method of claim 1 wherein the interconnect via comprises Co.

Assignees

• Globalfoundries Us Inc

Inventors

• Labonte Andre P
• Labelle Catherine B
• Park Chanro

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P50/28

  of insulating materials · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title