Gate tie-down enablement with inner spacer

Patent metadata

Field	Value
Publication number	US-10879375-B2
Application number	US-201916537095-A
Country	US
Kind code	B2
Filing date	Aug 9, 2019
Priority date	Aug 10, 2015
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.

First claim

The invention claimed is:

1. A gate tie-down structure, comprising:
a first gate structure including a first gate conductor disposed between spacer material including inner spacers formed on tops of respective first gate spacers to a height;
a second gate structure including a second gate conductor disposed between second gate spacers disposed to the height;
an interlevel dielectric (ILD) formed over the second gate structure and over a region adjacent to the second gate structure; and
a connection formed within the ILD over an active area connecting the first gate conductor and at least one of multiple trench contacts over at least one of the inner spacers.

2. The gate tie-down structure as recited in claim 1 , wherein the connection includes a self-aligned contact formed disposed on the at least one trench contact adjacent to one of the first gate spacers and a gate contact, the gate contact being in contact with the first gate conductor.

3. The gate tie-down structure as recited in claim 2 , wherein the first gate structure prevents contact between another one of the multiple trench contacts and the first gate conductor.

4. The gate tie-down structure as recited in claim 2 , wherein contact openings are filled with a first conductive material and the self-aligned contact includes a second conductive material.

5. The gate tie-down structure as recited in claim 1 , wherein the gate tie-down structure is formed in the active area to reduce device area.

6. The gate tie-down structure as recited in claim 1 , wherein the gate tie-down structure is included in a static random access memory.

7. The gate tie-down structure as recited in claim 1 , wherein the ILD includes a thickness above a cap layer of the second gate structure.

8. The gate tie-down structure as recited in claim 7 , wherein the cap layer includes a silicon nitride material.

9. The gate tie-down structure as recited in claim 1 , wherein the inner spacers are below the ILD.

10. A gate tie-down structure, comprising:
a first gate structure including a first gate conductor disposed between spacer material including inner spacers formed on tops of respective first gate spacers to a height;
a second gate structure including a second gate conductor disposed between second gate spacers disposed to the height; and
a connection, formed above a cap layer of the second gate structure, connecting between a contact on one side of the first gate structure and the first gate conductor over an active area and over one of the inner spacers.

11. The gate tie-down structure as recited in claim 10 , wherein the first gate structure prevents contact of the first gate conductor to a second contact on the other side of the first gate structure.

12. The gate tie-down structure as recited in claim 10 , wherein the contact includes a trench contact connected to a gate contact and the gate contact is self-aligned with the trench contact.

13. The gate tie-down structure as recited in claim 10 , wherein the gate tie-down structure is formed in the active area to reduce device area.

14. The gate tie-down structure as recited in claim 10 , wherein the contact includes a same material as the first and second gate conductors.

15. The gate tie-down structure as recited in claim 10 , wherein the gate tie-down structure is included in a static random access memory.

16. The gate tie-down structure as recited in claim 10 , wherein the first gate structure permits contact between a self-aligned contact and the contact and prevents contact between the trench contact and the first gate conductor.

17. A gate tie-down structure, comprising:
a first gate structure including a first gate conductor disposed between spacer material including inner spacers formed on tops of respective first gate spacers to a height; and
a second gate structure including a second gate conductor disposed between second gate spacers disposed to the height.

18. The gate tie-down structure of claim 17 , further comprising an interlevel dielectric (ILD) formed over the second gate structure and over a region adjacent to the second gate structure.

19. The gate tie-down structure of claim 17 , further comprising a connection connecting the first gate conductor and a trench contact over at least one of the inner spacers, wherein the first gate structure prevents contact between another trench contact and the first gate conductor.

20. The gate tie-down structure of claim 19 , wherein the connection includes a self-aligned contact disposed on the trench contact adjacent to one of the first gate spacers and a gate contact disposed on the first gate conductor.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Fan Su Chen
• Labonte Andre P
• Liebmann Lars W
• Mehta Sanjay C

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title