Interconnect structure having reduced resistance variation and method of forming same

Patent metadata

Field	Value
Publication number	US-10832944-B2
Application number	US-201816177854-A
Country	US
Kind code	B2
Filing date	Nov 1, 2018
Priority date	Nov 1, 2018
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

An interconnect structure of an integrated circuit and a method of forming the same, the interconnect structure including: at least two metal lines laterally spaced from one another in a dielectric layer, the metal lines having a top surface below a top surface of the dielectric layer; a hardmask layer on an upper portion of sidewalls of the metal lines, the hardmask layer having a portion extending between the metal lines, the extending portion being below the top surface of the metal lines; and at least one fully aligned via on the top surface of a given metal line.

First claim

We claim:

1. An interconnect structure of an integrated circuit, the interconnect structure comprising:
at least two metal lines laterally spaced from one another in a dielectric layer, the at least two metal lines having a top surface below a top surface of the dielectric layer;
a hardmask layer on an upper portion of sidewalls of the at least two metal lines, the hardmask layer having a portion extending between the at least two metal lines, the extending portion being below the top surface of the metal lines;
at least one fully aligned via on the top surface of a given metal line of the at least two metal lines; and
an etch stop layer having a first portion directly on the dielectric layer and a second portion directly on any portion of the at least two metal lines not having the at least one fully aligned via thereon, and surrounding the at least one fully aligned via.

2. The interconnect structure of claim 1 , further comprising:
an inter-layer dielectric (ILD) over the etch stop layer, the dielectric layer and the any portion of the at least two metal lines not having a via thereon, and surrounding the at least one fully aligned via.

3. The interconnect structure of claim 1 , wherein the at least one fully aligned via is wider than the given metal line thereunder.

4. The interconnect structure of claim 1 , wherein the dielectric layer includes a first dielectric layer below the hardmask layer portion extending between the at least two metal lines, and a second dielectric layer above the hardmask layer portion extending between the at least two metal lines.

5. The interconnect structure of claim 4 , wherein the first dielectric layer includes a first dielectric material and the second dielectric layer includes a second dielectric material, the first and second dielectric materials being different.

6. The interconnect structure of claim 1 , wherein the top surface of each of the at least two metal lines are coplanar and flat.

7. The interconnect structure of claim 1 , wherein the hardmask layer includes a dielectric material including silicon nitride (SiN), silicon dioxide (SiO 2 ), boron-doped silicon oxycarbonitride (SiOCBN), an aluminum oxide, or aluminum nitride (AlN).

8. The interconnect structure of claim 1 , wherein the at least two metal lines include copper.

9. An interconnect structure of an integrated circuit, the interconnect structure comprising:
a dielectric layer;
a pair of metal lines laterally spaced from one another within the dielectric layer, wherein each of the pair of metal lines includes a top surface below a top surface of the dielectric layer, and wherein the top surface of each of the pair of metal lines is coplanar and flat;
a hardmask layer on an upper portion of a sidewall of each of the pair of metal lines, the hardmask layer having a portion extending between the pair of metal lines and below the top surface of the metal lines;
at least one fully aligned via on the top surface of one of the pair of metal lines, wherein the at least one fully aligned via is wider than the one of the pair of metal lines; and
an etch stop layer having a first portion directly on the dielectric layer and a second portion directly on any portion of the at least two metal lines not having the at least one fully aligned via thereon, and surrounding the at least one fully aligned via.

10. The interconnect structure of claim 9 , further comprising:
an inter-layer dielectric (ILD) over the etch stop layer, the dielectric and any portion of the pair of metal lines not having a via thereon, and surrounding the at least one fully aligned via.

11. The interconnect structure of claim 9 , wherein the dielectric layer includes a first dielectric layer below the hardmask layer portion extending between the pair of metal lines, and a second dielectric layer above the hardmask layer portion extending between the pair of metal lines.

12. The interconnect structure of claim 11 , wherein the first dielectric layer includes a first dielectric material and the second dielectric layer includes a second dielectric material, the first and second dielectric materials being different.

13. The interconnect structure of claim 9 , wherein the hardmask layer includes a dielectric material including silicon nitride (SiN), silicon dioxide (SiO 2 ), boron-doped silicon oxycarbonitride (SiOCBN), an aluminum oxide, or aluminum nitride (AlN).

14. The interconnect structure of claim 9 , wherein each of the pair of metal lines includes copper.

15. An interconnect structure of an integrated circuit, the interconnect structure comprising:
a dielectric layer;
a pair of metal lines laterally spaced from one another within the dielectric layer, wherein each of the pair of metal lines includes a top surface below a top surface of the dielectric layer, and wherein the top surface of each of the pair of metal lines is coplanar and flat;
a hardmask layer on an upper portion of a sidewall of each of the pair of metal lines, the hardmask layer having a portion extending between the pair of metal lines and below the top surface of the metal lines;
at least one fully aligned via on the top surface of one of the pair of metal lines, wherein the at least one fully aligned via is wider than the one of the pair of metal lines;
an inter-layer dielectric (ILD) over the dielectric layer, over any portion of the pair of metal lines not having a via thereon, and surrounding the at least one fully aligned via; and
an etch stop layer between the ILD and the dielectric layer and between the ILD and the any portion of the pair of metal lines not having a via thereon.

16. The interconnect structure of claim 15 , wherein the dielectric layer includes a first dielectric layer below the hardmask layer portion extending between the pair of metal lines, and a second dielectric layer above the hardmask layer portion extending between the pair of metal lines.

17. The interconnect structure of claim 16 , wherein the first dielectric layer includes a first dielectric material and the second dielectric layer includes a second dielectric material, the first and second dielectric materials being different.

18. The interconnect structure of claim 15 , wherein the hardmask layer includes a dielectric material including silicon nitride (SiN), silicon dioxide (SiO 2 ), boron-doped silicon oxycarbonitride (SiOCBN), an aluminum oxide, or aluminum nitride (AlN).

Assignees

• Globalfoundries Inc

Inventors

• Licausi Nicholas V
• Park Chanro
• Xie Ruilong
• Labonte Andre P

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/098

  by filling between adjacent conductive parts · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title