Gate tie-down enablement with inner spacer

Patent metadata

Field	Value
Publication number	US-9941163-B2
Application number	US-201715618880-A
Country	US
Kind code	B2
Filing date	Jun 9, 2017
Priority date	Aug 10, 2015
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

First claim

The invention claimed is:

1. A method for forming a gate tie-down, comprising:
forming a first opening down to a trench contact on each side of a gate structure;
forming a second opening down to a gate conductor of the gate structure, wherein forming the first opening and the second opening includes opening up the ILD by performing an extreme ultraviolet (EUV) lithography using a same color lithography to form patterns for the gate contact and the self-aligned contact before etching;
forming a dielectric barrier between the first opening and the second opening; and
forming a conductive material in the second opening to form a gate contact and forming the conductive material in the first opening to form a self-aligned contact, with a horizontal connection within an ILD.

2. The method as recited in claim 1 , wherein the dielectric barrier permits contact between the self-aligned contact and the gate contact and prevent contact between the trench contact and the gate conductor.

3. The method as recited in claim 1 , wherein the forming the conductive material further includes forming the ILD on the gate conductor and the trench contacts and over other gate structures.

4. The method as recited in claim 3 , wherein the forming the conductive material further includes opening up the ILD to expose the trench contact on the one side of the gate structure and the gate conductor.

5. The method as recited in claim 4 , further comprising opening up the ILD including performing a lithography, etch, lithography, etch (LELE) procedure wherein one lithography and etch forms a contact hole for the self-aligned contact and the other lithography and etch forms a contact hole for the gate contact.

6. The method as recited in claim 4 , further comprising opening up the ILD including performing a lithography, freeze, lithography, etch (LFLE) procedure wherein one lithography forms a contact hole pattern for the self-aligned contact, which is frozen, and the other lithography forms a contact hole pattern for the gate contact before etching.

7. The method as recited in claim 1 , wherein the gate contact is self-aligned to the trench contact.

8. The method as recited in claim 1 , further comprising opening up a cap layer to expose the gate conductor.

9. The method as recited in claim 8 , wherein the ILD includes a thickness above the cap layer of gate structures and the horizontal connection is formed within the thickness of the ILD.

10. A method for forming a gate tie-down, comprising:
recessing gate sidewall spacers on a gate structure to expose a gate conductor;
forming a first opening down to a trench contact on each side of a gate structure;
forming a second opening down to a gate conductor of the gate structure, wherein forming the first opening and the second opening includes opening up the ILD by performing an extreme ultraviolet (EUV) lithography using a same color lithography to form patterns for the gate contact and the self-aligned contact before etching;
forming a dielectric barrier between the first opening and the second opening; and
forming a conductive material in the second opening to form a gate contact and forming the conductive material in the first opening to form a self-aligned contact; and
planarizing the conductive material and an ILD to form a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

11. The method as recited in claim 10 , wherein the dielectric barrier permits contact between the self-aligned contact and the gate contact and prevent contact between the trench contact and the gate conductor.

12. The method as recited in claim 10 , wherein the forming the conductive material further includes depositing the ILD on the gate conductor and over the gate structures.

13. The method as recited in claim 12 , wherein the forming the conductive material further includes opening the ILD to expose the trench contact on the one side of the gate structure and the gate conductor.

14. The method as recited in claim 13 , further comprising opening up the ILD including performing a lithography, etch, lithography, etch (LELE) procedure wherein one lithography and etch forms a contact hole for the self-aligned contact and the other lithography and etch forms a contact hole for the gate contact.

15. The method as recited in claim 13 , further comprising opening up the ILD including performing a lithography, freeze, lithography, etch (LFLE) procedure wherein one lithography forms a contact hole pattern for the self-aligned contact, which is frozen, and the other lithography forms a contact hole pattern for the gate contact before etching.

16. The method as recited in claim 13 , wherein the gate contact is self-aligned to the trench contact.

17. The method as recited in claim 10 , further comprising opening up a cap layer to expose the gate conductor.

18. The method as recited in claim 17 , wherein the ILD includes a thickness above the cap layer of gate structures and the horizontal connection is formed within the thickness of the ILD.

Assignees

• IBM
• Globalfoundries Inc
• Globalfoundries Inc

Inventors

• Fan Su Chen
• Labonte Andre P
• Liebmann Lars W
• Mehta Sanjay C

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title