Gate tie-down enablement with inner spacer

Patent metadata

Field	Value
Publication number	US-10128352-B2
Application number	US-201715432372-A
Country	US
Kind code	B2
Filing date	Feb 14, 2017
Priority date	Aug 10, 2015
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.

First claim

The invention claimed is:

1. A gate tie-down structure, comprising:
a gate structure including a gate conductor and recessed gate spacers recessed below a cap level;
inner spacers formed over the recessed gate spacers;
trench contacts formed in a trench contact region on sides of the gate structure;
an interlevel dielectric (ILD) having a first thickness formed over the gate structure and a second thickness formed in the trench contact region down to at least one of the trench contacts; and
a horizontal connection formed within the first thickness of the ILD over an active area connecting the gate conductor and at least one of the trench contacts over one of the inner spacers.

2. The structure as recited in claim 1 , wherein the gate spacers and the inner spacers permit contact between a self-aligned contact formed on one of the trench contacts adjacent to one of the gate spacers and a gate contact, which contacts the gate conductor.

3. The structure as recited in claim 2 , wherein the gate spacers and the inner spacers prevent contact between the other one of the trench contacts and the gate conductor.

4. The structure as recited in claim 2 , wherein the gate contact is self-aligned with the trench contact.

5. The structure as recited in claim 2 , wherein the self-aligned contact includes a same material as the gate conductor.

6. The structure as recited in claim 1 , wherein the gate tie-down structure is formed in the active area to reduce device area.

7. The structure as recited in claim 1 , wherein the inner spacers are formed vertically aligned above the gate spacers.

8. The structure as recited in claim 1 , wherein the gate tie-down structure is included in a static random access memory.

9. The structure as recited in claim 1 , wherein the ILD includes a thickness above a cap layer of the gate structure.

10. The structure as recited in claim 1 , wherein the ILD includes oxide.

11. A gate tie-down structure, comprising:
a gate structure including a gate conductor and recessed gate spacers recessed below a cap level;
inner spacers formed over the recessed gate spacers;
an interlevel dielectric (ILD) formed down to at least one trench contact in a trench contact region and over the gate structure; and
a horizontal connection, formed in an interlevel dielectric (ILD) thickness over the gate structure, connecting between a contact on one side of the gate structure and the gate conductor over an active area and over one of the inner spacers.

12. The structure as recited in claim 11 , wherein the gate spacers and the inner spacers prevent contact of the gate conductor to a second contact on the other side of the gate structure.

13. The structure as recited in claim 11 , wherein the contact includes a trench contact connected to a gate contact and the gate contact is self-aligned with the trench contact.

14. The structure as recited in claim 11 , wherein the gate tie-down structure is formed in the active area to reduce device area.

15. The structure as recited in claim 11 , wherein the inner spacers are formed vertically aligned above the gate spacers.

16. The structure as recited in claim 11 , wherein the contact includes a same material as the gate conductor.

17. The structure as recited in claim 11 , wherein the gate tie-down structure is included in a static random access memory.

18. The structure as recited in claim 11 , wherein the thickness of the ILD is above a cap layer of the gate structure.

19. The structure as recited in claim 18 , wherein the inner spacers are below the thickness of the ILD.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Fan Su Chen
• Labonte Andre P
• Liebmann Lars W
• Mehta Sanjay C

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title