Methods of forming a semiconductor device with a gate contact positioned above the active region

Patent metadata

Field	Value
Publication number	US-10204994-B2
Application number	US-201715477565-A
Country	US
Kind code	B2
Filing date	Apr 3, 2017
Priority date	Apr 3, 2017
Publication date	Feb 12, 2019
Grant date	Feb 12, 2019

Abstract

One illustrative device disclosed herein includes, among other things, a stepped conductive source/drain structure with a first recess defined therein and a stepped final gate structure with a second recess defined therein, wherein, when viewed from above, the second recess is axially and laterally offset from the first recess. In this example, the device also includes a layer of insulating material positioned above the stepped conductive source/drain structure and the stepped final gate structure, a conductive gate (CB) contact that is conductively coupled to the stepped final gate structure and a conductive source/drain (CA) contact that is conductively coupled to the stepped conductive source/drain structure.

First claim

What is claimed:

1. A transistor device positioned above an active region of a semiconducting substrate, the device comprising:
a stepped conductive source/drain structure with a first recess defined therein, said first recess being located vertically above a first area of said active region;
a stepped final gate structure with a second recess defined therein, said second recess being located vertically above a second area of said active region, wherein, when viewed from above, said second recess is axially and laterally offset from said first recess, and wherein said stepped conductive source/drain structure is positioned between said stepped final gate structure and a second gate structure of said transistor device and extends from a first sidewall spacer positioned adjacent to said stepped final gate structure to a second sidewall spacer positioned adjacent to said second gate structure;
a raised source/drain region positioned between said stepped final gate structure and said second gate structure, said raised source/drain region conductively coupling said stepped conductive source/drain structure to a source/drain region formed in said active region
a layer of insulating material positioned above said stepped conductive source/drain structure and said stepped final gate structure;
a conductive gate (CB) contact positioned in said layer of insulating material that is conductively coupled to an upper surface of said stepped final gate structure, wherein at least a portion of said conductive gate (CB) contact is positioned vertically above said active region; and
a conductive source/drain (CA) contact positioned in said layer of insulating material that is conductively coupled to said upper surface of said stepped conductive source/drain structure, wherein at least a portion of said conductive source/drain (CA) contact is positioned vertically above said active region.

2. The device of claim 1 , wherein an entirety of said conductive gate (CB) contact is positioned vertically above said active region.

3. The device of claim 1 , wherein said stepped conductive source/drain structure has a stepped configuration when viewed in cross-sectional view taken through said stepped conductive source/drain structure in a direction corresponding to a gate width direction of said transistor device and wherein said stepped final gate structure has a stepped configuration when viewed in cross-sectional view taken through said stepped final gate structure in a direction corresponding to a gate width direction of said transistor device.

4. The device of claim 1 , wherein said conductive gate (CB) contact is positioned laterally adjacent said first recess and separated therefrom by at least one non-conductive material.

5. The device of claim 1 , wherein said conductive source/drain (CA) contact is positioned laterally adjacent said second recess and separated therefrom by at least one non-conductive material.

6. The device of claim 1 , further comprising an insulating gate cap material positioned in said second recess.

7. The device of claim 1 , further comprising an insulating material positioned in said first recess.

8. The device of claim 1 , wherein said active region has an overall gate width dimension in a direction corresponding to a gate width direction of said transistor device, and wherein said first recess in said stepped conductive source/drain structure has an overall axial length in a gate width direction of said device that is approximately 20-60% of said overall gate width dimension of said active region.

9. The device of claim 1 , wherein said active region has an overall gate width dimension in a direction corresponding to a gate width direction of said transistor device, and wherein said second recess in said stepped final gate structure has an overall axial length in a gate width direction of said device that is approximately 40-80% of said overall gate width dimension of said active region.

10. The device of claim 1 , further comprising a silicon nitride sidewall spacer positioned between said stepped conductive source/drain structure and said stepped final gate structure and wherein said stepped conductive source/drain structure comprises a metal silicide material and a conductive metal positioned above said metal silicide material and wherein said stepped final gate structure comprises a high-k insulating material and at least one material comprising a metal.

11. The device of claim 1 , wherein said second recess extends across an upper surface of said stepped final gate structure from a first inside surface of said first sidewall spacer to a second inside surface of said first sidewall spacer that is opposite of said first inside surface.

12. The device of claim 1 , wherein said first recess extends across an upper surface of said stepped conductive source/drain structure from an outside surface of said first sidewall spacer to an outside surface of said second sidewall spacer.

13. A transistor device positioned above an active region of a semiconducting substrate, the transistor device comprising:
a stepped conductive source/drain structure with a first recess defined therein, said first recess being located vertically above a first area of said active region;
an insulating material positioned in said first recess;
a stepped final gate structure with a second recess defined therein, said second recess being located vertically above a second area of said active region, wherein, when viewed from above, said second recess is axially and laterally offset from said first recess;
a layer of insulating material positioned above said stepped conductive source/drain structure and said stepped final gate structure;
a conductive gate (CB) contact positioned in said layer of insulating material that is conductively coupled to an upper surface of said stepped final gate structure, wherein at least a portion of said conductive gate (CB) contact is positioned vertically above said active region; and
a conductive source/drain (CA) contact positioned in said layer of insulating material that is conductively coupled to said upper surface of said stepped conductive source/drain structure, wherein at least a portion of said conductive source/drain (CA) contact is positioned vertically above said active region.

14. The transistor device of claim 13 , wherein said stepped conductive source/drain structure has a stepped configuration when viewed in cross-sectional view taken through said stepped conductive source/drain structure in a direction corresponding to a gate width direction of said transistor device and wherein said stepped final gate structure has a stepped configuration when viewed in cross-sectional view taken through said stepped final gate structure in a direction corresponding to a gate width direction of said transistor device.

15. The transistor device of claim 13 , wherein said conductive gate (CB) contact is positioned laterally adjacent said first recess and separated therefrom by at least one non-conductive material, and wherein said conductive source/drain (CA) contact is positioned laterally adjacent said second recess and separated therefrom by at least one non-conductive material.

16. A transistor device positioned above an active region of a semiconducting substrate, the transistor device comprising:
a stepped conductive source/drain structure with a first recess defined therein, said first recess being located vertically above a first area of said active region;
a stepped final gate structure with a second recess defined therein, said second recess being located vertically above a second

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Park Chanro
• Labonte Andre P
• Liebmann Lars W
• Cave Nigel G
• Raymond Mark V
• Bouche Guillaume
• Brown David E

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title