Methods of forming variable-depth device structures

Patent metadata

Field	Value
Publication number	US-11112694-B2
Application number	US-202015931333-A
Country	US
Kind code	B2
Filing date	May 13, 2020
Priority date	May 15, 2019
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

A method for forming a device structure is disclosed. The method of forming the device structure includes forming a variable-depth structure in a device material layer using cyclic-etch process techniques. A plurality of device structures is formed in the variable-depth structure to define vertical or slanted device structures therein. The variable-depth structure and the vertical or slanted device structures are formed using an etch process.

First claim

What is claimed is:

1. A method, comprising:
forming a gray-tone resist over a device material, the forming the gray-tone resist comprising:
disposing a resist material over the device material; and
developing the resist material to form a gray-tone pattern;

performing a cyclic-etch process, the cyclic-etch process comprising:
etching a resist segment of the gray-tone pattern using a resist etch process selective to the resist material;
etching a device segment of the device material using a device pattern etch process selective to the device material; and
repeating the resist etch process for subsequent resist segments of the gray-tone pattern and etching subsequent device segments to form a device material pattern, the top surface of the device material pattern having a gradient;

disposing a hardmask over the device material;
patterning the hardmask to expose segments of the device material; and
etching exposed segments of the device material to form a plurality of device structures having a variable depth corresponding to the gradient.

2. The method of claim 1 , wherein the etching the exposed segments of the device material forms the plurality of device structures with slant angles relative to a lower surface of the device material that are less than or greater than 90 degrees.

3. The method of claim 2 , wherein the etching the exposed segments of the device material includes an angled etch process.

4. The method of claim 1 , wherein the etching the exposed segments of the device material forms the plurality of device structures substantially perpendicular to a lower surface of the device material.

5. The method of claim 4 , wherein the etching the exposed segments of the device material includes an isotropic etch process.

6. The method of claim 1 , wherein an etch stop layer is disposed at a lower surface of the device material.

7. The method of claim 1 , wherein forming the gray-tone pattern comprises laser ablation or a lithography process.

8. The method of claim 1 , wherein an etch selectivity of the resist material to the device material is about 10:1 to about 1000:1.

9. The method of claim 1 , wherein an etch selectivity of the device material to the resist material is about 1:1 to about 10:1.

10. The method of claim 1 , wherein the device material is a substrate.

11. The method of claim 1 , wherein the device material is a device material layer formed over a substrate.

12. The method of claim 1 , further comprising removing residual resist material and disposing the hardmask over the device material subsequent to removing the residual resist material.

13. A method, comprising:
disposing a device material layer over a surface of a substrate, the surface of the substrate having an etch stop layer;
disposing a hardmask over the device material layer and patterning the hardmask to expose segments of the device material layer;
forming a gray-tone resist over the hardmask, the forming the gray-tone resist comprising:
disposing a resist material over the hardmask; and
developing the resist material to form a gray-tone pattern; and

performing a cyclic-etch process, the cyclic-etch process comprising:
etching a resist segment of the gray-tone pattern using a resist etch process selective to the resist material;
etching an exposed segment of the device material layer using a device etch process selective to a device material of the device material layer; and
repeating the resist etch process for subsequent resist segments of the gray-tone pattern and repeating the device etch process for subsequent exposed device segments of the device material layer to form a plurality of device structures having a variable depth.

14. The method of claim 13 , wherein the device etch process includes an angled etch process, and wherein the device etch process forms the plurality of device structures with slant angles relative to the surface of the substrate that are less than or greater than 90 degrees.

15. The method of claim 13 , wherein forming the gray-tone pattern comprises laser ablation or a lithography process.

16. The method of claim 13 , wherein the device etch process includes an isotropic etch process, and wherein the device etch process forms the plurality of device structures substantially perpendicular to the surface of the substrate.

17. The method of claim 13 , wherein a depth of the plurality of device structures is less than a thickness of the device material.

18. The method of claim 13 , wherein an etch selectivity of the resist material to a device material of the device material layer is about 10:1 to about 1000:1.

19. The method of claim 13 , wherein an etch selectivity of the device material to the resist material is about 1:1 to about 10:1.

20. The method of claim 13 , wherein the device material layer includes one or more silicon oxycarbide (SiOC), titanium dioxide (TiO.sub.2), silicon dioxide (SiO.sub.2), vanadium (IV) oxide (VOx), aluminum oxide (Al.sub.2O.sub.3), indium tin oxide (ITO), zinc oxide (ZnO), tantalum pentoxide (Ta.sub.2O.sub.5), silicon nitride (Si.sub.3N.sub.4), zirconium dioxide (ZrO.sub.2), or silicon carbon-nitride (SiCN) containing materials.

21. A method, comprising:
disposing a hardmask over a surface of a substrate and patterning the hardmask to expose segments of the substrate;
forming a gray-tone resist over the hardmask, the forming the gray-tone resist comprising:
disposing a resist material over the hardmask; and
developing the resist material to form a gray-tone pattern using laser ablation; and

performing a cyclic-etch process, the cyclic-etch process comprising:
etching a resist segment of the gray-tone pattern using a resist etch process selective to the resist material;
etching an exposed segment of the substrate using a device etch process selective to the substrate material; and
repeating the resist etch process for subsequent resist segments of the gray-tone pattern and repeating the device etch process to exposed segments of the substrate material layer to form a plurality of device structures in the substrate having a variable depth.

22. The method of claim 21 , wherein the substrate includes one or more silicon oxycarbide (SiOC), titanium dioxide (TiO.sub.2), silicon dioxide (SiO.sub.2), vanadium (IV) oxide (VOx), aluminum oxide (Al.sub.2O.sub.3), indium tin oxide (ITO), zinc oxide (ZnO), tantalum pentoxide (Ta.sub.2O.sub.5), silicon nitride (Si.sub.3N.sub.4), zirconium dioxide (ZrO.sub.2), or silicon carbon-nitride (SiCN) containing materials.

23. The method of claim 21 , wherein the device etch process includes an angled etch process, and wherein the device etch process forms the plurality of device structures with slant angles relative to the surface of the substrate that are less than or greater than 90 degrees.

24. The method of claim 21 , wherein forming the gray-tone pattern comprises laser ablation or a lithography process.

25. The method of claim 21 , wherein the device etch process includes an isotropic etch process, and wherein the device etch process forms the plurality of device structures substantially perpendicular to the surface of the substrate.

26. The method of claim 21 , wherein an etch selectivity of the resist material to a device material of the device material layer is about 10:1 to about 1000:1.

27. The method of claim 21 , wherein an etch selectivity of the device

Assignees

• Applied Materials Inc

Inventors

• Labonte Andre P
• Godet Ludovic
• Meyer Timmerman Thijssen Rutger

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P50/28

  of insulating materials · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title