Interconnect structure without barrier layer on bottom surface of via
US-2025279315-A1 · Sep 4, 2025 · US
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Kuo Tz-Jun patents
Kuo Tz-Jun is listed as an inventor on 30 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Kuo Tz-Jun |
| Total patents | 30 |
| First publication | Jan 15, 2015 |
| Latest publication | Sep 4, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Interconnect structure without barrier layer on bottom surface of via
US-12308282-B2 · May 20, 2025 · US
Method of forming metal interconnection
US-11715689-B2 · Aug 1, 2023 · US
Via structure and methods for forming the same
US-11551967-B2 · Jan 10, 2023 · US
Via structure and methods for forming the same
US-2022352012-A1 · Nov 3, 2022 · US
Interconnect Structure without Barrier Layer on Bottom Surface of Via
US-2022262675-A1 · Aug 18, 2022 · US
Interconnect structure without barrier layer on bottom surface of via
US-11322391-B2 · May 3, 2022 · US
Via structure and methods for forming the same
US-2021366765-A1 · Nov 25, 2021 · US
Method of Forming Metal Interconnection
US-2020343177-A1 · Oct 29, 2020 · US
Method of forming metal interconnection
US-10714424-B2 · Jul 14, 2020 · US
Recent patents
Latest publications not already listed above.
Interconnect structure without barrier layer on bottom surface of via
US-2020035546-A1 · Jan 30, 2020 · US
Interconnect structure without barrier layer on bottom surface of via
US-10453740-B2 · Oct 22, 2019 · US
Method of Forming Metal Interconnection
US-2019115297-A1 · Apr 18, 2019 · US
Interconnect structure without barrier layer on bottom surface of via
US-2019006230-A1 · Jan 3, 2019 · US
Method of forming metal interconnection
US-10163786-B2 · Dec 25, 2018 · US
Method of forming metal interconnection
US-9972529-B2 · May 15, 2018 · US
Method of forming an interconnection
US-9842767-B2 · Dec 12, 2017 · US
Method for Via Plating with Seed Layer
US-2017236750-A1 · Aug 17, 2017 · US
Method of Forming Metal Interconnection
US-2017186685-A1 · Jun 29, 2017 · US
Method for via plating with seed layer
US-9640431-B2 · May 2, 2017 · US
Method of forming metal interconnection
US-9613856-B1 · Apr 4, 2017 · US
Method of Forming Metal Interconnection
US-2017092536-A1 · Mar 30, 2017 · US
Method of Forming Metal Interconnection
US-2017084483-A1 · Mar 23, 2017 · US
Method for Via Plating with Seed Layer
US-2016240434-A1 · Aug 18, 2016 · US
Back end of the line (BEOL) interconnect scheme
US-9343356-B2 · May 17, 2016 · US
Method for via plating with seed layer
US-9324608-B2 · Apr 26, 2016 · US
Method for Via Plating with Seed Layer
US-2015255334-A1 · Sep 10, 2015 · US
Method for via plating with seed layer
US-9054163-B2 · Jun 9, 2015 · US
Method for Via Plating with Seed Layer
US-2015126030-A1 · May 7, 2015 · US
Method of semiconductor integrated circuit fabrication
US-2015017799-A1 · Jan 15, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Taiwan Semiconductor Mfg Co Ltd | 27 |
| Taiwan Semiconductor Mfg | 4 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W20/057 | 27 |
| H10W20/056 | 25 |
| H10W20/425 | 23 |
| H10W20/076 | 21 |
| H10W20/034 | 20 |