Method of forming metal interconnection

Patent metadata

Field	Value
Publication number	US-9972529-B2
Application number	US-201514867872-A
Country	US
Kind code	B2
Filing date	Sep 28, 2015
Priority date	Sep 28, 2015
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A method of fabricating a semiconductor device is disclosed. The method includes forming a first conductive feature over a substrate, forming a dielectric layer over the first conductive feature, forming a via trench in the dielectric layer, forming a first barrier layer in the via trench. Therefore the first barrier has a first portion disposed over the dielectric layer and a second portion disposed over the first conductive feature, applying a thermal treatment to convert the first portion of the barrier layer to a second barrier layer and exposing the first conductive feature in the via trench while a portion of the second barrier layer is disposed over the dielectric layer.

First claim

What is claimed is:

1. A method comprising:
forming a first conductive feature in a semiconductor substrate, wherein the first conductive feature has a first sidewall and an opposing second sidewall and a first barrier layer is disposed along the first and second sidewalls such that the first conductive feature is separated from the semiconductor substrate by the first barrier layer;
forming a dielectric layer over the first conductive feature and the first barrier layer;
forming a via trench in the dielectric layer, wherein a portion of the first conductive feature and a portion of the first barrier layer are exposed within the via trench;
forming a second barrier layer in the via trench directly on the dielectric layer, the portion of the first barrier layer and the portion of the first conductive feature, wherein the second barrier layer has a first portion disposed directly on the dielectric layer and a second portion disposed directly on the portion of the first conductive feature and the portion of the first barrier layer, wherein the second barrier layer is formed of manganese nitride;
applying a thermal treatment to convert the first portion of the second barrier layer to a third barrier layer, wherein the third barrier layer and manganese nitride have different etching selectivity;
exposing the portion of the first conductive feature in the via trench by removing the second portion of the second barrier layer while the first portion of the second barrier layer is disposed directly on the dielectric layer; and
after the exposing the portion of the first conductive feature, forming a second conductive feature directly on the third barrier layer and the first conductive feature such that an interface between the first and second conductive features is free of manganese nitride.

2. The method of claim 1 , wherein after applying the thermal treatment to convert the first portion to the third barrier layer, the second portion of the second barrier layer remains the same such that the third barrier layer is formed of a different material than the second portion of the second barrier layer.

3. The method of claim 1 , wherein applying the thermal treatment to convert the first portion to the third barrier layer includes applying the thermal treatment to the second portion of the second barrier layer to chemically change a composition of the second portion of the second barrier layer such that the second portion of the second barrier layer is different than the third barrier layer.

4. The method of claim 1 , wherein applying the thermal treatment to convert the first portion of the second barrier layer to the third barrier layer includes converting the manganese nitride to MnSixOyNz, where x represents Si composition in atomic percent, y represents oxygen composition in atomic percent and z represents nitrogen composition in atomic percent.

5. The method of claim 1 , wherein the third barrier layer is disposed along the first sidewall and the opposing second sidewall of the via trench, and
wherein the second conductive feature is formed of a conductive material that physically contacts the first conductive feature and extends continuously from the third barrier layer disposed along the first sidewall to the third barrier layer disposed along the second sidewall.

6. The method of claim 1 , wherein forming the second barrier layer in the via trench includes forming the second barrier layer directly on a top surface of the dielectric layer, the top surface of the dielectric layer facing away from the substrate.

7. A method comprising:
forming a dielectric layer over a first conductive feature disposed in a semiconductor substrate, wherein the first conductive feature is surrounded by a first barrier layer in the semiconductor substrate;
forming a trench in the dielectric layer, wherein a portion of the first conductive feature and a portion of the first barrier layer are exposed within the trench;
forming a second barrier layer in the trench directly on the dielectric layer, the portion of the first barrier layer and the portion of the first conductive feature, wherein a first portion of the second barrier layer is formed along a sidewall surface of the trench defined by the dielectric layer and a second portion of the second barrier layer is formed along a bottom surface of the trench defined by the first conductive feature, the second barrier layer comprising manganese nitride;
converting the first portion of the second barrier layer into a third barrier layer, wherein the third barrier layer and manganese nitride have different etching selectivity;
exposing the first conductive feature in the trench by removing the second portion of the second barrier layer while a portion of the third barrier layer is disposed over the dielectric layer; and
forming a second conductive feature in the trench directly on the third barrier layer and the first conductive feature such that an interface between the first and second conductive features is free of manganese nitride.

8. The method of claim 7 , wherein converting the first portion of the second barrier layer into the third barrier layer includes performing an annealing process on the second barrier layer.

9. The method of claim 7 , wherein after converting the first portion of the second barrier layer into the third barrier layer the second portion of the second barrier layer remains the same such that the third barrier layer is formed of a different material than the second portion of the second barrier layer.

10. The method of claim 7 , wherein the third barrier layer includes MnSixOyNz, where x represents Si composition in atomic percent, y represents oxygen composition in atomic percent and z represents nitrogen composition in atomic percent.

11. The method of claim 7 , wherein exposing the first conductive feature in the trench includes removing the second portion of the second barrier layer by performing a wet etch process that includes an acid.

12. The method of claim 7 , wherein forming the second conductive feature in the trench includes:
forming a conductive layer in the trench directly on the first conductive feature; and
planarizing the conductive layer to form the second conductive feature.

13. The method of claim 7 , wherein a third portion of the second barrier layer is formed along another sidewall surface of the trench defined by the dielectric layer, the another sidewall surface opposing the sidewall surface,
wherein converting the first portion of the second barrier layer into the third barrier layer includes converting the third portion of the second barrier into the third barrier layer,
wherein the third barrier layer is disposed along a sidewall surface and the another sidewall surface, and
wherein the second conductive feature is formed of a conductive material that physically contacts the first conductive feature and extends continuously from the third barrier layer disposed along the sidewall surface to the third barrier layer disposed along the another sidewall surface.

14. The method of claim 8 , wherein the anneal process is selected from a group consisting of a rapid thermal anneal process, a laser anneal process, a furnace anneal process, and a flash lamp anneal process.

15. The method of claim 8 , wherein a temperature range of the anneal process is from about 100° C. to about 400° C.

16. The method of claim 7 , wherein the portion of the first barrier layer has a top surface facing away from the substrate, and
wherein forming the second barrier layer in the trench directly on the portion of the first barrier laye

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Shin-Yi
• Lee Ming-Han
• Shue Shau-Lin
• Kuo Tz-Jun

Classifications

• H10W20/0552

  by diffusing metallic dopants to react with dielectrics · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/034

  bottomless barrier, adhesion or liner layers · CPC title

• H10W20/033

  in openings in dielectrics · CPC title