Back end of the line (BEOL) interconnect scheme

Patent metadata

Field	Value
Publication number	US-9343356-B2
Application number	US-201313771175-A
Country	US
Kind code	B2
Filing date	Feb 20, 2013
Priority date	Feb 20, 2013
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

The present disclosure relates to a method of forming a back-end-of-the-line metal interconnect layer. The method is performed by depositing one or more self-assembled monolayers on a semiconductor substrate to define a metal interconnect layer area. A metal interconnect layer having a plurality of metal structures is formed on the semiconductor substrate within the metal interconnect layer area. An inter-level dielectric layer is then formed onto the surface of the semiconductor substrate in areas between the plurality of metal structures.

First claim

What is claimed is:

1. A method of forming a metal back-end-of-the-line interconnect layer, comprising:
selectively depositing a first self-assembled monolayer (SAM) contacting an underlying first inter-level dielectric (ILD) layer;
selectively depositing a second self-assembled monolayer (SAM) on an underlying metal interconnect layer laterally surrounded by the first ILD layer; and
removing a portion of the first SAM or the second SAM to form a metal interconnect layer area, wherein the first SAM or the second SAM is removed by using a photomask to selectively expose the first SAM or the second SAM to an ultraviolet radiation pattern that degrades a portion of the first SAM or a portion of the second SAM;
selectively depositing a metal interconnect layer comprising a plurality of metal structures within the metal interconnect layer area; and
depositing a second inter-level dielectric layer in areas between the plurality of metal structures.

2. The method of claim 1 , wherein the first SAM comprises:
a head group comprising trichlorosilicon (SiCl 3 ) or trimethoxysilane (Si(OCH 3 ) 3 );
an alkyl chain; and
a terminal group comprising a methyl group.

3. The method of claim 1 , wherein the second SAM comprises:
a head group comprising sulfhydryl or thiol;
an alkyl chain; and
a terminal group comprising a methyl group.

4. The method of claim 1 , wherein the metal interconnect layer comprises a copper metal or alloy deposited by an electroless plating process.

5. The method of claim 4 , further comprising:
depositing a metal catalyst layer that is confined along a planar surface within the metal interconnect layer area.

6. The method of claim 4 , further comprising:
inserting an alloy dopant into the copper metal during the electroless plating process, wherein the alloy dopant is configured to react with the second inter-level dielectric layer to form a self-forming barrier layer positioned between the metal interconnect layer and the second inter-level dielectric layer.

7. The method of claim 6 , wherein the alloy dopant comprises one or more of: magnesium (Mg), aluminum (Al), chromium (Cr), manganese (Mn), titanium (Ti), zirconium (Zr), silver (Ag), niobium (Nb), boron (B), indium (In), tin (Sn), and molybdenum (Mo).

8. The method of claim 6 , further comprising:
performing an annealing process after forming the second inter-level dielectric layer, wherein the annealing process forms the self-forming barrier layer.

9. The method of claim 1 , wherein the first SAM and the second SAM respectively comprise an ordered assembly of organic molecules having a head group connected to a terminal group by a molecular chain.

10. A method of forming a back-end-of-the-line (BEOL) metal interconnect layer, comprising:
selectively depositing a first self-assembled monolayer (SAM) on an underlying first inter-level dielectric layer located over a substrate;
selectively depositing a second self-assembled monolayer (SAM) on an underlying metal interconnect layer located over the substrate;
selectively exposing the first SAM or the second SAM to radiation, wherein the radiation degrades a portion of the first SAM or the second SAM;
removing the degraded portion of the first SAM or the second SAM;
forming a first metal interconnect layer comprising one or more metal structures in areas exposed to the radiation;
selectively forming a second inter-level dielectric layer onto the substrate in areas between the one or more metal structures; and
annealing the substrate after forming the second inter-level dielectric layer, wherein annealing the substrate forms a self-forming barrier layer between the one or more metal structures and second inter-level dielectric layer.

11. The method of claim 10 , further comprising:
selectively depositing a layer of palladium after removing a degraded portion of the first SAM or the second SAM.

12. The method of claim 10 , further comprising:
forming one or more additional self-assembled monolayers over the first metal interconnect layer and the second inter-level dielectric layer;
selectively exposing one or more of the one or more additional self-assembled monolayers to additional radiation; and
forming an additional metal interconnect layer in areas exposed to the additional radiation.

13. The method of claim 12 , further comprising:
selectively depositing a third inter-level dielectric layer in areas between a plurality of metal structures of the additional metal interconnect layer.

14. A method of forming a metal back-end-of-the-line interconnect layer, comprising:
depositing a plurality of self-assembled monolayers onto an underlying metal interconnect layer and an underlying ILD layer, which are arranged over a semiconductor substrate and that have upper surfaces aligned along a plane;
removing a portion of one or more of the plurality of self-assembled monolayers to form a metal interconnect layer area, wherein the portion of the one or more of the plurality of the self-assembled monolayers is removed by using a photomask to selectively expose the portion of the one or more of the plurality of the self-assembled monolayers to an ultraviolet radiation pattern that degrades the portion of the one or more of the plurality of the self-assembled monolayers;
selectively forming a metal interconnect layer comprising a plurality of metal structures within the metal interconnect layer area; and
depositing a second inter-level dielectric layer over the semiconductor substrate in areas between the plurality of metal structures.

15. The method of claim 14 , wherein the metal interconnect layer is deposited by an electroless plating process.

16. The method of claim 15 , further comprising:
inserting an alloy dopant into the metal interconnect layer during the electroless plating process, wherein the alloy dopant is configured to react with the second inter- level dielectric layer to form a self-forming barrier layer positioned between the metal interconnect layer and the second inter-level dielectric layer.

17. The method of claim 16 , wherein the alloy dopant comprises one or more of: magnesium (Mg), aluminum (Al), chromium (Cr), manganese (Mn), titanium (Ti), zirconium (Zr), silver (Ag), niobium (Nb), boron (B), indium (In), tin (Sn), and molybdenum (Mo).

18. The method of claim 14 , wherein the plurality of self- assembled monolayers are deposited to a thickness that is substantially equal.

19. The method of claim 14 , wherein depositing the plurality of self-assembled monolayers, comprises:
selectively depositing a first self-assembled monolayer (SAM) on the underlying ILD layer overlying the semiconductor substrate;
selectively depositing a second self-assembled monolayer (SAM) on the underlying metal interconnect layer disposed within the underlying ILD layer;
using a photomask to selectively expose the first SAM and the second SAM to an ultraviolet radiation pattern, wherein the ultraviolet radiation pattern degrades a portion of the first SAM or a portion of the second SAM; and
removing the degraded portion the first SAM or the second SAM.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kuo Chi-Liang
• Kuo Tz-Jun
• Lee Hsiang-Huan

Classifications

• H10W20/4424 Primary

  Copper alloys · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title