Method for via plating with seed layer

US9324608B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9324608-B2
Application numberUS-201514720264-A
CountryUS
Kind codeB2
Filing dateMay 22, 2015
Priority dateNov 6, 2013
Publication dateApr 26, 2016
Grant dateApr 26, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a structure, comprising: forming a via opening in a dielectric layer; forming a seed layer on a sidewall of the via opening; forming a metallic protection layer over the seed layer; and simultaneously removing the metallic protection layer and depositing a via layer on the seed layer. 2. The method of claim 1 , wherein the metallic protection layer is removed by exposure to a electroplating solution. 3. The method of claim 1 , wherein the electroplating solution comprises an acid. 4. The method of claim 1 , further comprising chemical mechanical polishing a top surface of the via layer to form a conductive via. 5. The method of claim 1 wherein the protection layer comprises a metallic material. 6. The method of claim 5 , wherein the electroplating solution comprises an ionic metal at a concentration by weight between about 2.0% and about 3.7%, the ionic metal deposited on the seed layer to form the via layer. 7. The method of claim 6 , wherein the metallic protection layer has a reduction-oxidation potential lower than a material of the ionic metal. 8. The method of claim 6 , wherein the ionic metal is copper, and the protection layer comprises at least one of manganese, cobalt, titanium, aluminum, vanadium, chromium, zinc, zirconium, or oxides of the same. 9. The method of claim 1 , wherein the seed layer and protection layer remain substantially free of oxidation. 10. A method, comprising: providing a substrate having a dielectric layer formed over a trace; forming a via opening extending through the dielectric layer, the via opening exposing a surface of the trace; forming a seed layer in the via opening and contacting the trace; forming a conductive protection layer over the seed layer; and simultaneously removing the protection layer and depositing a via layer on the seed layer in a single plating process step. 11. The method of claim 10 , wherein the step of simultaneously removing the protection layer and depositing a via layer includes exposing the protection layer to an electroplating solution. 12. The method of claim 11 , wherein the plating solution is an electroplating solution and comprises an acid, and wherein the acid removes the metallic protection layer during the forming the via layer. 13. The method of claim 11 , wherein the electroplating solution has a pH of less than about 6. 14. The method of claim 11 , wherein the electroplating solution comprises an ionic metal at a concentration by weight between about 2.0% and about 3.7%, the ionic metal deposited on the seed layer to form the via layer. 15. The method of claim 11 , wherein the metallic protection layer has a reduction-oxidation potential lower than a material of the ionic metal. 16. The method of claim 14 , wherein forming the via layer comprises electroplating the ionic metal onto the seed layer using an electroplating voltage sufficient to deposit the ionic metal faster than the acid of the electroplating solution removes a material from the via layer. 17. The method of claim 14 , wherein the protection layer comprises a material selected from the group consisting of manganese, cobalt, titanium, aluminum, vanadium, chromium, zinc, zirconium, oxides of the same, and alloys of the same. 18. A method of forming a structure, comprising: forming a plurality of intermetal dielectrics (IMDs) having at least one via disposed through a dielectric layer, forming each of the plurality of IMDs comprising: forming a seed layer in the via opening and contacting a metal feature below the dielectric layer; forming a protection layer over the seed layer; simultaneously removing the protection layer and forming a via layer in the via opening and in contact with the seed layer by applying an electroplating solution in the via opening; and forming a metallization layer over at least one of the plurality of IMDs. 19. The method of claim 18 , wherein the protection layer comprises a material selected from the group consisting of manganese, cobalt, titanium, aluminum, vanadium, chromium, zinc, zirconium, oxides of the same, and alloys of the same. 20. The method of claim 18 , wherein the electroplating solution removes the protection layer and forms a metal via layer on the seed layer.

Assignees

Inventors

Classifications

  • using a liquid · CPC title

  • of electrodes ohmically coupled to a semiconductor · CPC title

  • Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

  • by forming openings in the dielectric parts · CPC title

  • by selectively depositing, e.g. by using selective CVD or plating · CPC title

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What does patent US9324608B2 cover?
Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed l…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd, Taiwan Semiconductor Mfg
What technology area does this patent fall under?
Primary CPC classification H10W20/043. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 26 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).