Interconnect structure without barrier layer on bottom surface of via

Patent metadata

Field	Value
Publication number	US-10453740-B2
Application number	US-201715679385-A
Country	US
Kind code	B2
Filing date	Aug 17, 2017
Priority date	Jun 29, 2017
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.

First claim

What is claimed is:

1. An interconnect structure for a semiconductor device, comprising:
a layer of conductive material;
a layer of insulating material formed on the layer of conductive material;
a via filled with a first metal formed in the layer of insulating material and disposed on the layer of conductive material, wherein the first metal is in contact with the layer of insulating material;
a first trench conductor formed above the via and in the layer of insulating material;
a second trench conductor formed in the layer of insulating material, wherein:
the second trench conductor is laterally displaced from the via;
bottom surfaces of the first and second trench conductors are coplanar with each other; and
the layer of conductive material extends below the first and the second trench conductors; and

a trench barrier in contact with the first trench conductor.

2. The interconnect structure of claim 1 , wherein the trench barrier is in contact with a top surface of the first metal.

3. The interconnect structure of claim 1 , wherein a top surface of the trench barrier is coplanar with a top surface of the second trench conductor.

4. The interconnect structure of claim 1 , further comprising another trench barrier interposed between the second trench conductor and the layer of insulating material, wherein the another trench barrier is separated from the layer of conductive material by the layer of insulating material.

5. The interconnect structure of claim 1 , wherein each of the layer of conductive material, the first metal, the first trench conductor, and the second trench conductor comprises copper (Cu), cobalt (Co), nickel (Ni), ruthenium (Ru), rhodium (Rh), iridium (Ir), osmium (Os), aluminum (Al), indium (In), silver (Ag), gold (Au), tungsten (W), carbon nanotubes, or any combination thereof.

6. The interconnect structure of claim 1 , wherein each of the layer of conductive material, the first metal, the first trench conductor, and the second trench conductor comprises metals alloyed with boron (B), aluminum (Al), titanium (Ti), chromium (Cr), manganese (Mn), niobium (Nb), palladium (Pd), silver (Ag), indium (In), tin (Sn), zinc (Zn), magnesium (Mg), gold (Au), or any combination thereof.

7. The interconnect structure of claim 1 , wherein the trench barrier comprises a metal, a metal alloy, a metal nitride, a carbon containing material, a metal oxide, an organo-silane, or an organo-phosphane.

8. The interconnect structure of claim 1 , wherein the trench barrier comprises a self-forming barrier formed by reactions between the layer of insulating material and the trench conductor during a thermal treatment process.

9. The interconnect structure of claim 1 , wherein the trench barrier has a thickness between about 1 Å and about 50 Å.

10. An interconnect structure for a semiconductor device, comprising:
a layer of a first conductive material;
a layer of insulating material above the layer of the first conductive material;
a via conductor comprising a metal material, wherein the metal material is in contact with the layer of the first conductive material and the layer of insulating material; and
first and second trench conductors formed in the layer of insulating material, wherein:
each of the first and the second trench conductors comprises a second conductive material and a trench barrier;
the trench barrier of the first trench conductor is above the via conductor;
the trench barrier of the second trench conductor is separated from the via conductor by the layer of insulating material; and
the layer of the first conductive material extends below the first and second trench conductors.

11. The interconnect structure of claim 10 , wherein the second conductive material is separated from the layer of the first conductive material by the layer of insulating material.

12. The interconnect structure of claim 10 , wherein the first trench conductor is separated from the second trench conductor by the layer of insulating material.

13. The interconnect structure of claim 12 , wherein the trench barrier of each of the first and the second trench conductors comprises:
a metal comprising tantalum (Ta);
a metal alloy comprising titanium tungsten (TiW);
a metal oxide comprising alumina, manganese oxide, manganese silicon oxide (MnSiO x ), chromium oxide, niobium oxide or titanium oxide;
a metal nitride comprising tantalum nitride (TaN) or titanium nitride (TiN); or
an organic compound comprising an organo-silane, an organo-phosphane, or a carbon-containing material.

14. The interconnect structure of claim 12 , wherein bottom surfaces of the trench barriers of the first and the second trench conductors are coplanar with each other.

15. The interconnect structure of claim 10 , wherein the insulating material comprises silicon dioxide, silicon nitride, silicon oxy-nitride, or any combination thereof.

16. The interconnect structure of claim 10 , wherein the second conductive material of the first trench conductor is disposed over the via conductor.

17. The interconnect structure of claim 10 , further comprising another layer of insulating material underlying the layer of the first conductive material.

18. An interconnect structure for a semiconductor device, comprising:
a conductive layer;
an insulating layer disposed above the conductive layer;
a first trench conductor disposed in the insulating layer, wherein the first trench conductor is separated from the conductive layer by the insulating layer; and
a second trench conductor disposed in the insulating layer, wherein:
a first portion of the second trench conductor is in contact with the conductive layer and the insulating layer;
a second portion of the second trench conductor is disposed over the first portion of the second trench conductor; and
a trench barrier disposed between the first and the second portions of the second trench conductor,

wherein the conductive layer extends below the first and the second trench conductors.

19. The interconnect structure of claim 18 , wherein the trench barrier is in contact with the insulating layer.

20. The interconnect structure of claim 18 , wherein a ratio between a height and a width of at least one of the first and second trench conductors is between about 0.5 and about 100.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kuo Tz-Jun
• Ho Chien-Hsin
• Lee Ming-Han

Classifications

• H10W20/0552

  by diffusing metallic dopants to react with dielectrics · CPC title

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/076

  in via holes or trenches · CPC title