Method of forming metal interconnection

Patent metadata

Field	Value
Publication number	US-11715689-B2
Application number	US-202016927328-A
Country	US
Kind code	B2
Filing date	Jul 13, 2020
Priority date	Sep 18, 2015
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a first conductive feature;
a dielectric layer disposed on a top surface of the first conductive feature;
a second conductive feature disposed directly over the first conductive feature and extending through the dielectric layer to directly contact the first conductive feature; and
a barrier layer disposed between the second conductive feature and the dielectric layer but extending between the first conductive feature and the second conductive feature,
wherein the barrier layer includes a semiconductor element of the dielectric layer.

2. The integrated circuit device of claim 1 , wherein the barrier layer and the dielectric layer each interface with the top surface of the first conductive feature.

3. The integrated circuit device of claim 1 , wherein the second conductive feature includes a via portion disposed on the first conductive feature and an upper portion disposed on the via portion.

4. The integrated circuit device of claim 3 , wherein the upper portion of the second conductive feature physically contacts the via portion.

5. The integrated circuit device of claim 3 , wherein the barrier layer is disposed on side and bottom surfaces of the upper portion of the second conductive feature.

6. The integrated circuit device of claim 1 , wherein the barrier layer is a first barrier layer, the integrated circuit device further comprising a second barrier layer disposed alongside the first conductive feature, wherein the first barrier layer and the second barrier layer are different in composition.

7. The integrated circuit device of claim 6 , wherein the first barrier layer includes silicon, oxygen, and at least one material from a group consisting of: manganese, manganese nitride, titanium, tantalum, cobalt, cobalt tungsten, or molybdenum; and
wherein the second barrier layer includes at least one material from a group consisting of: titanium nitride, tantalum nitride, tungsten nitride, titanium silicon nitride, and tantalum silicon nitride.

8. The integrated circuit device of claim 1 , wherein the barrier layer includes a first vertical portion and a second vertical portion disconnected from the first vertical portion at an interface between the second conductive feature and the first conductive feature.

9. A device, comprising:
a first conductive feature;
a dielectric layer disposed on a top surface of the first conductive feature;
a second conductive feature disposed directly over the first conductive feature and extending through the dielectric layer to directly contact the first conductive feature; and
a barrier layer disposed between the second conductive feature and the dielectric layer but not extending between the first conductive feature and the second conductive feature, wherein the barrier layer comprises manganese, silicon, oxygen, and nitrogen.

10. The device of claim 9 ,
wherein the first conductive feature is disposed in a lower dielectric layer,
wherein the first conductive feature is spacer part from the lower dielectric layer by a lower barrier layer,
wherein a composition of the lower barrier layer is different from a composition of the barrier layer.

11. The device of claim 10 , wherein the lower barrier layer comprises titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN) and/or tantalum silicon nitride (TaSiN).

12. The device of claim 9 , further comprising a bottom barrier layer disposed between the second conductive feature and the first conductive feature,
wherein a composition of the bottom barrier layer is different from a composition of the barrier layer.

13. The device of claim 12 , wherein the bottom barrier layer comprises manganese nitride.

14. The device of claim 9 ,
wherein the second conductive feature comprises a lower via portion and an upper line portion disposed over the lower via portion,
wherein a portion of the barrier layer is disposed between the upper line portion and the dielectric layer along a vertical direction.

15. A structure, comprising:
a first conductive feature disposed in a first dielectric layer;
a second dielectric layer disposed on a top surface of the first conductive feature and a top surface of the first dielectric layer;
a second conductive feature disposed directly over the first conductive feature and extending through the second dielectric layer to directly contact the first conductive feature; and
a barrier layer disposed between the second conductive feature and the second dielectric layer but not extending between the first conductive feature and the second conductive feature,
wherein the barrier layer comprises manganese, manganese nitride, titanium, tantalum, cobalt, cobalt tungsten, or molybdenum,
wherein the second conductive feature comprises a lower via portion and an upper line portion disposed over the lower via portion.

16. The structure of claim 15 ,
wherein the lower via portion comprises a first width,
wherein the upper line portion comprises a second width such that a portion of the upper line portion overhangs the lower via portion.

17. The structure of claim 16 , wherein a bottom surface of the barrier layer is coplanar with a bottom surface of the second conductive feature.

18. The structure of claim 15 ,
wherein the first conductive feature is spaced apart from the first dielectric layer by a lower barrier layer,
wherein a composition of the lower barrier layer is different from a composition of the barrier layer.

19. The structure of claim 18 ,
wherein the lower barrier layer comprises titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN), or tantalum silicon nitride (TaSiN).

20. The structure of claim 15 ,
wherein the first conductive feature comprises aluminum (Al), copper (Cu), or tungsten (W),
wherein the second conductive feature comprises copper (Cu), copper manganese (CuMn), copper aluminum (CuAl), copper titanium, (CuTi), copper vanadium (CuV), copper chromium (CuCr), copper silicon (CuSi), or copper niobium (CuNb).

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Shin-Yi
• Lee Ming-Han
• Shue Shau-Lin
• Kuo Tz-Jun

Classifications

• H10W20/0552

  by diffusing metallic dopants to react with dielectrics · CPC title

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4432

  the principal metal being a noble metal, e.g. gold · CPC title

• H10W20/4424

  Copper alloys · CPC title