Method of forming an interconnection

Patent metadata

Field	Value
Publication number	US-9842767-B2
Application number	US-201414299089-A
Country	US
Kind code	B2
Filing date	Jun 9, 2014
Priority date	Sep 21, 2012
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a plurality of openings is formed on the substrate. A barrier layer is deposited in the openings by a first tool and a sacrificing protection layer is deposited on the barrier layer by the first tool. The sacrificing layer is removed and a metal layer is deposited on the barrier layer by a second tool.

First claim

What is claimed is:

1. A method comprising:
forming a patterned dielectric layer having an opening on a substrate, wherein a first layer is exposed by the opening;
depositing a barrier layer in the opening, wherein after depositing the barrier layer in the opening a portion of the first layer is exposed within the opening;
depositing a material layer on the barrier layer in the opening, wherein the material layer includes a metal component;
removing the material layer, including the metal component, to expose the entire barrier layer within the opening;
after removing the material layer to expose the entire barrier layer within the opening, depositing a seed layer on the exposed barrier layer, wherein after depositing the seed layer on the exposed barrier layer, the portion of the first layer is exposed within the opening; and
after depositing the seed layer on the exposed barrier layer, depositing a metal layer on the seed layer without exposing the barrier layer to an oxidation ambient.

2. The method of claim 1 , wherein the material layer is deposited on the barrier layer without exposing the barrier layer to an oxidation ambient.

3. The method of claim 1 , further comprising forming a doped region in the substrate, and
wherein the seed layer is deposited directly over the doped region.

4. The method of claim 1 , further comprising forming a conductive feature in the substrate, and
wherein the metal layer physically contacts the conductive feature.

5. The method of claim 4 , wherein the conductive feature includes a metal material.

6. The method of claim 1 , wherein forming the patterned dielectric layer having the opening on the substrate includes depositing a first dielectric material layer and a second dielectric material layer and patterning the first and second dielectric material layers.

7. The method of claim 1 , wherein the metal component includes a metal oxide.

8. A method comprising:
forming a first dielectric layer having a first opening over a substrate, wherein a first layer is exposed by the first opening;
forming a second dielectric layer having a second opening over the first dielectric layer;
depositing a barrier layer in the first and second openings, wherein after depositing the barrier layer in the first and second openings a portion of the first layer is exposed within the first opening;
depositing a material layer on the barrier layer in the first and second openings, wherein the material layer includes a metal component;
removing the material layer, including the metal component, to expose the entire barrier layer within the first and second openings;
after removing the material layer to expose the entire barrier layer within the first and second openings, depositing a seed layer on the exposed barrier layer, wherein after depositing the seed layer on the exposed barrier layer, the portion of the first layer is exposed within the first opening; and
after depositing the seed layer on the exposed barrier layer, depositing a metal layer on the seed layer without exposing the barrier layer to an oxidation ambient.

9. The method of claim 8 , wherein the second opening directly over the first opening such that the second opening is in communication with the first opening.

10. The method of claim 9 , wherein the first opening has a first width and the second opening has a second width that is different than the first width.

11. The method of claim 8 , wherein the barrier layer includes one or more metals from the group consisting of tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), cobalt (Co), tungsten nitride (WN), titanium silicon nitride (TiSiN), and tantalum silicon nitride (TaSiN).

12. The method of claim 8 , wherein the metal component includes one or more metals selected from the group consisting of manganese (Mn), cobalt (Co) and aluminum (Al).

13. The method of claim 8 , wherein the metal component includes metal compounds selected from the group consisting of manganese oxide (MnOx), cobalt oxide (CoOx) and aluminum oxide (AlOx), where x represents oxide composition in atomic percent.

14. The method of claim 8 , wherein depositing the barrier layer in the first and second openings includes depositing the barrier layer by a first tool; and
wherein removing the material layer to expose the barrier layer includes removing the material layer by a second tool that is different than the first tool.

15. The method of claim 8 , wherein the material layer is deposited on the barrier layer without exposing the barrier layer to an oxidation ambient.

16. A method comprising:
forming a patterned dielectric layer with an opening on a substrate, wherein a first layer is exposed by the opening;
depositing a barrier layer in the opening, wherein after depositing the barrier layer in the opening a portion of the first layer is exposed within the opening;
depositing a metal material layer on the barrier layer in the opening, wherein the metal material layer includes a metal component;
removing the metal material layer, including the metal component, to expose the entire barrier layer within the opening;
after removing the metal material layer to expose the entire barrier layer, depositing a metal seed layer on the exposed barrier layer, wherein after depositing the seed layer on the exposed barrier layer, the portion of the first layer is exposed within the opening; and
after depositing the metal seed layer on the exposed barrier layer, depositing a metal layer on the metal seed layer within the opening and without exposing the barrier layer to an oxidation ambient.

17. The method of claim 16 , further comprising forming a conductive feature in the substrate, and
wherein the metal layer physically contacts the conductive feature.

18. The method of claim 17 , wherein the conductive feature is a silicide feature.

19. The method of claim 17 , wherein the conductive feature is another metal feature.

20. The method of claim 16 , wherein the metal component includes a metal oxide.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Ming-Han
• Kuo Tz-Jun
• Ho Chien-Hsin
• Lee Hsiang-Huan

Classifications

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

• H10W20/4424 Primary

  Copper alloys · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title