Interconnect structure without barrier layer on bottom surface of via

Patent metadata

Field	Value
Publication number	US-12308282-B2
Application number	US-202217734683-A
Country	US
Kind code	B2
Filing date	May 2, 2022
Priority date	Jun 29, 2017
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.

First claim

What is claimed is:

1. A method, comprising:
forming an insulating layer over a first conductive layer;
forming a via opening in the insulating layer to expose a portion of the first conductive layer;
forming a sacrificial layer on the portion of the first conductive layer;
forming a first portion of a barrier layer on the sacrificial layer and a second portion of the barrier layer over a sidewall of the via opening;
removing the first portion of the barrier layer and sacrificial layer to expose the portion of the first conductive layer, wherein removing the sacrificial layer comprises selectively etching the sacrificial layer with an organic solvent in a lift-off process; and
filling the via opening with a second conductive layer.

2. The method of claim 1 , wherein forming the first and second portions of the barrier layer comprises forming the first and second portions of the barrier layer by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a physical vapor deposition (PVD) process at a temperature ranging from about 10° C. to about 400° C.

3. The method of claim 1 , wherein filling the via opening with the second conductive layer comprises filling the via opening with a metal from a bottom of the via opening to a top of the via opening.

4. The method of claim 1 , wherein filling the via opening with the second conductive layer comprises depositing a cobalt-containing compound, and wherein the cobalt-containing compound comprises a carbonyl group and an organic ligand.

5. The method of claim 1 , further comprising:
forming a trench opening in the insulating layer and above the via opening; and
forming a trench barrier layer on the second conductive layer and over a sidewall of the trench opening.

6. The method of claim 5 , wherein forming the trench barrier layer comprises depositing a metal, a metal compound, a carbon-containing material, and combinations thereof.

7. The method of claim 1 , further comprising:
forming a trench opening in the insulating layer and above the via opening; and
filling the trench opening with a third conductive layer.

8. The method of claim 7 , wherein filling the trench opening with the third conductive layer comprises:
depositing a metal in the trench opening; and
planarizing the metal by a chemical mechanical planarization (CMP) process.

9. The method of claim 1 , further comprising forming a trench opening in the insulating layer and above the via opening, wherein filling the via opening with the second conductive layer comprises filling the via opening and the trench opening with the second conductive layer by a dual damascene process.

10. A method, comprising:
forming an insulating layer over a first conductive layer;
forming a via-plus-trench opening in the insulating layer to expose a portion of the first conductive layer;
forming a monolayer on the portion of the first conductive layer and a sidewall of the via-plus-trench opening;
forming a barrier layer on the sidewall of the via-plus-trench opening, wherein the monolayer inhibits formation of the barrier layer on a bottom surface of the via-plus-trench opening and enhances the formation of the barrier layer on the sidewall of the via-plus-trench opening;
filling a via portion of the via-plus-trench opening with a second conductive layer; and
filling a trench portion of the via-plus-trench opening with a third conductive layer.

11. The method of claim 10 , wherein filling the via portion of the via-plus-trench opening with the second conductive layer comprises filling the via portion of the via-plus-trench opening with a metal in a bottom-up process.

12. The method of claim 10 , further comprising forming a trench barrier layer on the second conductive layer and over a sidewall of the trench portion of the via-plus-trench opening.

13. The method of claim 10 , further comprising forming the monolayer by a vapor phase or a liquid phase process.

14. The method of claim 10 , further comprising forming the barrier layer at a temperature between about 10° C. and about 400° C.

15. A method, comprising:
forming an insulating layer over a first conductive layer;
forming a via opening in the insulating layer to expose a portion of the first conductive layer;
forming a monolayer on the portion of the first conductive layer and on a sidewall of the via opening;
forming a barrier layer over a sidewall of the via opening, wherein the monolayer inhibits formation of the barrier layer on portion of the first conductive layer and enhances the formation of the barrier layer on the sidewall of the via opening; and
filling the via opening with a second conductive layer, wherein the second conductive layer is a cobalt-containing compound comprising a carbonyl group and an organic ligand.

16. The method of claim 15 , further comprising:
forming a trench opening in the insulating layer and above the via opening;
forming a trench barrier on the second conductive layer and over a sidewall of the trench opening;
depositing a third conductive layer in the trench opening; and
planarizing the third conductive layer by a chemical mechanical planarization (CMP) process.

17. The method of claim 16 , further comprising forming the trench barrier at a temperature between about 10° C. and about 400° C.

18. The method of claim 15 , further comprising forming a trench opening in the insulating layer and above the via opening, wherein filling the via opening with the second conductive layer comprises filling the via opening and the trench opening with the second conductive layer by a dual damascene process.

19. The method of claim 15 , further comprising forming another monolayer on the portion of the first conductive layer.

20. The method of claim 15 , further comprising forming the monolayer by a vapor phase or a liquid phase process.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kuo Tz-Jun
• Ho Chien-Hsin
• Lee Ming-Han

Classifications

• H10W20/0552

  by diffusing metallic dopants to react with dielectrics · CPC title

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/076

  in via holes or trenches · CPC title