Method for via plating with seed layer

Patent metadata

Field	Value
Publication number	US-9640431-B2
Application number	US-201615138033-A
Country	US
Kind code	B2
Filing date	Apr 25, 2016
Priority date	Nov 6, 2013
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.

First claim

What is claimed is:

1. A method of forming a structure, comprising:
forming an opening in a material layer;
lining the opening with a metallic protection layer; and
simultaneously removing the metallic protection layer and depositing a conductor in the opening.

2. The method of claim 1 , wherein the step of forming an opening in a material layer includes etching an opening in a dielectric layer.

3. The method of claim 2 , wherein the opening includes a trench opening, a via opening, or both.

4. The method of claim 1 , further comprising lining the opening with a seed layer before the step of lining the opening with a metallic protection layer.

5. The method of claim 1 , wherein the step of simultaneously removing the metallic protection layer and depositing a conductor in the opening includes submersing the metallic protection layer in an electroplating solution.

6. The method of claim 1 , wherein the metallic protection layer protects an underlying material from oxidation during subsequent process steps.

7. The method of claim 1 , wherein the metallic protection layer has a lower reduction-oxidation potential than the conductor.

8. The method of claim 1 , wherein the conductor comprises copper and the metallic protection layer is a material selected from the group consisting of manganese (Mn), cobalt (Co), titanium (Ti), aluminum (Al), vanadium (V), chromium (Cr), zinc (Zn), zirconium (Zr), and alloys or oxides of the same.

9. A method comprising:
forming a conductive trace in an integrated circuit;
depositing a dielectric layer over the conductive trace;
patterning the dielectric layer to form an opening therein, the opening exposing at least a portion of the conductive trace;
lining the opening with a seed layer;
depositing a protection layer over the seed layer;
submersing the protection layer and the seed layer in an electroplating solution; and
filling the lined opening with a conductor while removing the protection layer using an acidic component of the electroplating solution.

10. The method of claim 9 , further comprising depositing an etch stop layer over the conductive trace before depositing the dielectric layer.

11. The method of claim 9 , wherein the seed layer is a metal selected from the group consisting of copper, aluminum, titanium, gold manganese, and alloys thereof.

12. The method of claim 9 , wherein the protection layer is selected from the group consisting of manganese (Mn), cobalt (Co), titanium (Ti), aluminum (Al), vanadium (V), chromium (Cr), zinc (Zn), zirconium (Zr), and alloys or oxides of the same.

13. The method of claim 9 , wherein the acidic component comprises sulfuric acid that removes the protection layer.

14. The method of claim 9 , further comprising maintaining the seed layer in an inert environment until after the protection layer is deposited.

15. The method of claim 9 , wherein the step of lining the opening with a seed layer and the step of depositing a protection layer over the seed layer both occur in a same processing chamber in an inert environment.

16. The method of claim 9 , wherein the seed layer is deposited substantially free of oxidation.

17. A method, comprising:
forming a material layer on a workpiece;
forming an opening in the material layer;
lining the opening with a seed layer;
covering the seed layer with a metallic protection layer; and
subjecting the workpiece to a plating process, wherein the metallic protection layer is removed and a conductor is plated on the seed layer in a single process chamber.

18. The method of claim 17 , wherein the step of subjecting the workpiece to a plating process comprises submersing the workpiece in an electroplating solution.

19. The method of claim 18 , wherein the electroplating solution includes an acidic component that removes the metallic protection layer.

20. The method of claim 17 , wherein the metallic protection layer is a material selected from the group consisting of manganese (Mn), cobalt (Co), titanium (Ti), aluminum (Al), vanadium (V), chromium (Cr), zinc (Zn), zirconium (Zr), and alloys or oxides of the same.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Shin-Yi
• Yeh Ching-Fu
• Kuo Tz-Jun
• Lee Hsiang-Huan
• Lee Ming-Han

Classifications

• H10P14/46

  using a liquid · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title