Memory Circuitry And Methods Used In Forming Memory Circuitry
US-2026089934-A1 · Mar 26, 2026 · US
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Gambee Christopher J patents
Gambee Christopher J is listed as an inventor on 36 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Gambee Christopher J |
| Total patents | 36 |
| First publication | May 19, 2015 |
| Latest publication | Mar 26, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Die features for self-alignment during die bonding
US-11302653-B2 · Apr 12, 2022 · US
Devices with three-dimensional structures and support elements to increase adhesion to substrates
US-11276658-B2 · Mar 15, 2022 · US
Edge cut debond using a temporary filler material with no adhesive properties and edge cut debond using an engineered carrier to enable topography
US-11094684-B2 · Aug 17, 2021 · US
Reduction of roughness on a sidewall of an opening
US-10923478-B2 · Feb 16, 2021 · US
Semiconductor devices having discretely located passivation material, and associated systems and methods
US-10896886-B2 · Jan 19, 2021 · US
Die Features for Self-Alignment During Die Bonding
US-2020373252-A1 · Nov 26, 2020 · US
Devices three-dimensional structures to substrates
US-2020365542-A1 · Nov 19, 2020 · US
Methods of fabricating conductive traces and resulting structures
US-10811313-B2 · Oct 20, 2020 · US
Methods for enhancing adhesion of three-dimensional structures to substrates
US-10790251-B2 · Sep 29, 2020 · US
Recent patents
Latest publications not already listed above.
Die features for self-alignment during die bonding
US-10748857-B2 · Aug 18, 2020 · US
Reduction of roughness on a sidewall of an opening
US-2020243535-A1 · Jul 30, 2020 · US
Die Features for Self-Alignment During Die Bonding
US-2020083178-A1 · Mar 12, 2020 · US
Methods for enhancing adhesion of three-dimenional structures to substrates, and related assemblies and systems
US-2019393176-A1 · Dec 26, 2019 · US
Edge Cut Debond Using a Temporary Filler Material With No Adhesive Properties and Edge Cut Debond Using an Engineered Carrier to Enable Topography
US-2019341378-A1 · Nov 7, 2019 · US
Edge cut debond using a temporary filler material with no adhesive properties and edge cut debond using an engineered carrier to enable topography
US-10403618-B2 · Sep 3, 2019 · US
Methods of fabricating conductive traces and resulting structures
US-2019259660-A1 · Aug 22, 2019 · US
Methods of fabricating conductive traces and resulting structures
US-10332792-B1 · Jun 25, 2019 · US
Semiconductor devices having discretely located passivation material, and associated systems and methods
US-2019189576-A1 · Jun 20, 2019 · US
Methods of fabricating conductive traces and resulting structures
US-2019189507-A1 · Jun 20, 2019 · US
Semiconductor devices having discretely located passivation material, and associated systems and methods
US-10262961-B2 · Apr 16, 2019 · US
Edge Cut Debond Using a Temporary Filler Material With No Adhesive Properties and Edge Cut Debond Using an Engineered Carrier to Enable Topography
US-2019088637-A1 · Mar 21, 2019 · US
Semiconductor devices having discretely located passivation material, and associated systems and methods
US-2019051623-A1 · Feb 14, 2019 · US
Semiconductor devices having discretely located passivation material, and associated systems and methods
US-10002840-B1 · Jun 19, 2018 · US
Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods
US-9966347-B2 · May 8, 2018 · US
Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods
US-2017287857-A1 · Oct 5, 2017 · US
Semiconductor devices and methods for backside photo alignment
US-9741612-B2 · Aug 22, 2017 · US
Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods
US-9704781-B2 · Jul 11, 2017 · US
Semiconductor devices and methods for backside photo alignment
US-2016172242-A1 · Jun 16, 2016 · US
Semiconductor structures comprising at least one through-substrate via filled with conductive materials
US-9318438-B2 · Apr 19, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 36 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W72/952 | 18 |
| H10W72/019 | 18 |
| H10W90/00 | 18 |
| H10W20/20 | 15 |
| H10W72/01938 | 14 |