Die features for self-alignment during die bonding

Patent metadata

Field	Value
Publication number	US-10748857-B2
Application number	US-201816127769-A
Country	US
Kind code	B2
Filing date	Sep 11, 2018
Priority date	Sep 11, 2018
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

First claim

What is claimed is:

1. A semiconductor device assembly comprising:
a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad, wherein the at least one dummy pad has a first area and the at least one electrical pad has a second area, the first area being at least two times as large as the second area:
a first semiconductor device having a first side and a second side;
at least one electrical pillar extending from the second side of the first semiconductor device, the at least one electrical pillar connected to the at least one electrical pad via solder to form an electrical interconnect between the first semiconductor device and the substrate;
at least one dummy pillar extending from the second side of the first semiconductor device;
a first liquid positioned between an end of the at least one dummy pillar and the at least one dummy pad, wherein a surface tension of the first liquid pulls the at least one dummy pillar towards the at least one dummy pad.

2. The semiconductor device assembly of claim 1 , wherein the surface tension of the first liquid reduces a warpage of the first semiconductor device.

3. The semiconductor device assembly of claim 1 , wherein the surface tension of the first liquid aligns the at least one dummy pillar with the at least one dummy pad.

4. The semiconductor device assembly of claim 1 , wherein the first liquid is solder and the at least one dummy pad is a dummy metal pad.

5. The semiconductor device assembly of claim 1 , wherein the at least one dummy pad is positioned within a recess on the first side of the substrate.

6. The semiconductor device assembly of claim 5 , wherein the recess is a recess within a solder mask layer on the first side of the substrate.

7. The semiconductor device assembly of claim 1 , wherein the first side of the first semiconductor device includes at least one dummy pad and at least one electrical pad.

8. The semiconductor device assembly of claim 7 , comprising:
a second semiconductor device having a first side and a second side;
at least one electrical pillar extending from the second side of the second semiconductor device, the at least one electrical pillar extending from the second side of the second semiconductor device connected via solder to the at least one electrical pad on the first side of the first semiconductor device to form an electrical interconnect between the first semiconductor device and the second semiconductor device;
at least one dummy pillar extending from the second side of the second semiconductor device;
a liquid positioned between an end of the at least one dummy pillar extending from the second surface of the second semiconductor device and the at least one dummy pad on the first surface of the first semiconductor device, wherein a surface tension of the liquid pulls the at least one dummy pillar extending from the second semiconductor device towards the at least one dummy pad on the first semiconductor device.

9. The semiconductor device assembly of claim 8 , wherein the surface tension of the second liquid aligns the second semiconductor device with the first semiconductor device.

10. The semiconductor device assembly of claim 9 , wherein the surface tension of the second liquid reduces a warpage of the second semiconductor device.

11. The semiconductor device assembly of claim 1 , wherein the fluid differs from the solder that connects the at least one electrical pillar connected to the at least one electrical pad.

12. The semiconductor device assembly of claim 1 , wherein the fluid is water, glycerol, diiodomethane, formamide, epoxy resin, or a combination thereof.

13. A semiconductor device comprising:
a substrate having a first side and a second side, the first side having an area;
a plurality of electrical pads on the first side, each of the plurality of electrical pads configured to be connected to an electrical pillar to form an electrical interconnect; and
a plurality of dummy pads on the first side, each of the plurality of dummy pads configured to be aligned with a plurality of pillars via surface tension of a fluid to be positioned between each of the plurality of dummy pads and a corresponding pillar of the plurality of pillars, wherein the fluid is water, glycerol, diiodomethane, formamide, epoxy resin, or a combination thereof.

14. The semiconductor device of claim 13 , wherein the plurality of dummy pads have a combined area that is at least ⅛ as large as the area of the first side of the substrate.

15. The semiconductor device of claim 13 , wherein the surface tension of the fluid applies a force that is greater than a warpage force of the substrate at a predetermined temperature.

16. The semiconductor device of claim 15 , wherein the predetermined temperature is 200 degrees Celsius or higher.

Assignees

• Micron Technology Inc

Inventors

• Street Bret K
• Zhou Wei
• Gambee Christopher J
• Hacker Jonathan S
• Luo Shijian

Classifications

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W72/856

  Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15) · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/07336

  Soldering or alloying · CPC title