Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods

Patent metadata

Field	Value
Publication number	US-9966347-B2
Application number	US-201715624493-A
Country	US
Kind code	B2
Filing date	Jun 15, 2017
Priority date	Nov 19, 2013
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

First claim

We claim:

1. A method for forming under-bump metal (UBM) structures on a semiconductor die, comprising:
forming a mask on a seed structure, wherein the mask has openings that expose areas of the seed structure that are electrically coupled to interconnects that extend at least partially through a semiconductor substrate;
plating a first material onto the exposed areas of the seed structure;
depositing a second material into the openings over the first material thereby forming a UBM pillar, wherein the second material is different than the first material, and the second material has a higher galvanic nobility than the first material;
forming a suppressant material on the second material;
removing at least a portion of the mask thereby exposing portions of the seed structure between the UBM pillars; and
removing the exposed portions of the seed structure between the UBM pillars by wet etching the seed structure and thereby forming UBM structures on the semiconductor die, wherein the galvanic suppressant inhibits corrosion of the first material caused by the difference in galvanic nobility between the second and first materials.

2. The method of claim 1 wherein:
the seed structure comprise at least copper;
plating the first material comprises plating copper onto the seed structure;
depositing the second material comprises depositing palladium into the openings; and
forming the suppressant material on the second material comprises forming a galvanic passivation material on the palladium that reduces the electrical potential of the palladium compared to without the galvanic passivation material.

3. The method of claim 2 wherein forming a galvanic passivation material comprises oxidizing the surface of the palladium using an O 2 ash process in an atmosphere including argon, nitrogen and oxygen at a pressure of 12 mT and a chuck temperature of 40° C.

4. The method of claim 1 wherein forming the suppressant material reduces an atomic percentage of palladium and increases an atomic percentage of oxide at an outer surface of the UBM structure.

5. The method of claim 1 , further comprising depositing an intermediate material onto the first material before depositing the second material into the openings, and subsequently depositing the second material onto the intermediate material.

6. The method of claim 5 wherein the first material comprises copper, the intermediate material comprises nickel, and the second material comprises palladium.

7. A method for forming under-bump metal (UBM) structures on a semiconductor die, comprising:
constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material, wherein the first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential;
reducing a difference in electrical potential between a surface of the second material and the first material; and
removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

8. The method of claim 7 wherein:
the seed structure comprise at least copper;
plating the first material comprises plating copper onto the seed structure;
depositing the second material comprises depositing palladium into the openings; and
reducing the difference in electrical potential comprises forming a suppressant material on the second material.

9. The method of claim 8 wherein forming a suppressant material comprises forming a galvanic passivation material on the palladium that passivates a surface of the palladium.

10. The method of claim 9 wherein forming a galvanic passivation material comprises oxidizing the surface of the palladium using an O 2 ash process in an atmosphere including argon, nitrogen and oxygen at a pressure of 12 mT and a chuck temperature of 40° C.

11. The method of claim 7 wherein reducing the difference in electrical potential comprises forming a suppressant material that reduces an atomic percentage of palladium and increases an atomic percentage of oxide at an outer surface of the UBM structure.

12. The method of claim 7 , further comprising depositing an intermediate material onto the first material before depositing the second material into the openings, and subsequently depositing the second material onto the intermediate material such that the UBM pillar has a copper/nickel/palladium structure.

13. The method of claim 12 wherein the first material comprises copper, the intermediate material comprises nickel, and the second material comprises palladium such that the UBM pillar has a nickel/palladium structure.

14. The method of claim 7 wherein the first material comprises nickel and the second material comprises palladium, and wherein the palladium is deposited directly on the nickel.

15. The method of claim 7 wherein removing second areas of the seed structure between the UBM pillars comprises performing a wet etch that undercuts the first material of the UBM pillar.

16. The method of claim 15 wherein the undercut has a depth that is less than 50% of a depth of another undercut of the first material without reducing the difference in electrical potential.

17. The method of claim 7 wherein:
the seed structure comprises a copper seed material, the first material comprises copper, and the second material comprises palladium;
the UBM structure has a cross-sectional dimension;
removing the second areas of the seed structure between the UBM pillars comprises performing a wet etch that removes the copper seed material between the UBM pillars and undercuts the copper first material; and
the undercut of the copper first material had a depth less than approximately 10% of the cross-sectional dimension of the UBM pillar.

18. The method of claim 7 wherein:
the seed structure comprises a copper seed material, the first material comprises copper, and the second material comprises palladium;
the UBM structure has a cross-sectional dimension;
removing the second areas of the seed structure between the UBM pillars comprises performing a wet etch that removes the copper seed material between the UBM pillars and undercuts the copper first material; and
the undercut of the copper first material had a depth less than approximately 20% of the cross-sectional dimension of the UBM pillar.

19. A method of forming a structure on a semiconductor die, comprising:
forming a first material having a first electrical potential;
forming a second material having a second electrical potential, wherein the second material is electrically coupled to the first material;
forming a suppressor material on the surface of the second material thereby reducing a difference in electrical potential between the surface of the second material and the first material; and
exposing the first material to an electrolyte, wherein the suppressor material inhibits corrosion of the first material in the presence of the electrolyte.

20. The method of claim 19 wherein the first material comprises copper, the second material comprises palladium, and the suppressor material comprises an oxide of the palladium.

21. The method of claim 19 wherein the structure comprises an underbump metal structure formed on a through-substrate via.

Assignees

• Micron Technology Inc

Inventors

• Wirz Brandon P
• Gandhi Jaspreet S
• Gambee Christopher J
• Yeldandi Satish

Classifications

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/934

  Cross-sectional shape, i.e. in side view · CPC title