Methods of fabricating conductive traces and resulting structures

Patent metadata

Field	Value
Publication number	US-10811313-B2
Application number	US-201916397683-A
Country	US
Kind code	B2
Filing date	Apr 29, 2019
Priority date	Dec 14, 2017
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

A method of forming conductive traces comprises forming a seed material over a surface of a substrate, forming a patterned mask material over the seed material to define trenches leaving portions of the seed material within the trenches exposed, and depositing a conductive material over the exposed seed material in the trenches to form conductive traces. At least a portion of the patterned mask material is removed, a barrier formed over side surfaces and upper surfaces of the conductive traces, and exposed portions of the seed material are removed. Conductive traces and structures incorporating conductive traces are also disclosed.

First claim

What is claimed is:

1. A structure, comprising:
conductive traces located over a substrate;
a seed material positioned between the conductive traces and the substrate;
wherein the conductive traces comprise a copper core configured with a rectangular cross-section, having smooth side surfaces having a mirror finish and a smooth upper surface having a mirror finish extending between the side surfaces and the seed material has a width less than a width of the conductive traces; and
a metal barrier extending over the upper surface and along the side surfaces of the copper core and stopping at a level of a lower surface of the copper core extending between the side surfaces and opposite the upper surface.

2. The structure of claim 1 , wherein the metal barrier comprises nickel, gold, tantalum, cobalt, indium, TiN, vanadium or a combination thereof.

3. The structure of claim 1 , wherein the smooth upper surface and the smooth side surfaces of the copper core exhibit a topography variation of no more than about 2 nanometers (nm) RMS.

4. The structure of claim 1 , wherein the conductive traces and a dielectric material comprise a redistribution layer (RDL), and further comprising at least one semiconductor die electrically connected to at least some of the conductive traces on one side of the RDL.

5. The structure of claim 4 , further comprising conductive elements electrically connected to at least some of the conductive traces on a side of the RDL opposite the at least one semiconductor die.

6. The structure of claim 1 , wherein the seed material is laterally recessed from the side surfaces of the copper core.

7. A structure, comprising:
conductive traces on a seed material, the conductive traces comprising a copper core having side surfaces and a first surface opposite the seed material, wherein the side surfaces and the first surface each comprise a smooth surface;
wherein the seed material has a lateral width less than a lateral width of the first surface of the conductive traces; and
a second set of conductive traces over the conductive traces, the second set of conductive traces operatively coupled to the conductive traces through interconnects.

8. The structure of claim 7 , wherein the smooth surface comprises a surface having a topography variation of no more than 2 nanometers RMS.

9. The structure of claim 7 , wherein the seed material comprises copper and, optionally, an under layer of titanium.

10. The structure of claim 7 , wherein the conductive traces further comprise a barrier material over the side surfaces and the first surface of the copper core.

11. The structure of claim 10 , wherein the barrier material comprises a material selected from the group consisting of nickel, gold, tantalum, cobalt, indium, TiN, vanadium or a combination thereof.

12. The structure of claim 7 , the second set of conductive traces comprising a second copper core comprising side surfaces and an upper surface opposite the interconnects.

13. The structure of claim 12 , the second set of conductive traces further comprising a barrier material over the side surfaces and the upper surface of the second set of conductive traces.

14. A structure, comprising:
a substrate;
a first elongated conductive trace over the substrate, the first elongated conductive trace comprising a conductive core having a rectangular cross-section, wherein the conductive core is covered on at least three sides by a metal barrier;
a second elongated conductive trace over the substrate, the second elongated conductive trace comprising a conductive core having a rectangular cross-section, wherein the conductive core is covered on at least three sides by a metal barrier; and
a seed material positioned between the substrate and at least one of the first elongated conductive trace and the second elongated conductive trace, wherein the metal barrier extends along a vertical side of the conductive core of each of the first elongated conductive trace and the second elongated conductive trace and terminates at a base of the conductive core of each of the first elongated conductive trace and the second elongated conductive trace;
wherein the first elongated conductive trace is electrically isolated from the second elongated conductive trace.

15. The structure of claim 14 , wherein a lateral width of the seed material is less than a lateral width of the conductive core of the at least one of the first elongated conductive trace the second elongated conductive trace.

16. The structure of claim 14 , wherein the metal barrier of at least one of the first elongated conductive trace and the second elongated conductive trace comprises a material selected from the group consisting of nickel, gold, tantalum, cobalt, indium, TiN, vanadium or a combination thereof.

17. The structure of claim 14 , wherein the conductive core of at least one of the first elongated conductive trace and the second elongated conductive trace comprises copper.

18. The structure of claim 14 , wherein the at least three sides of the conductive core of at least one of the first elongated conductive trace and the second elongated conductive trace exhibit a mirror finish.

Assignees

• Micron Technology Inc

Inventors

• Gambee Christopher J

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/247

  Dispositions of multiple bumps · CPC title