Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods

Patent metadata

Field	Value
Publication number	US-9704781-B2
Application number	US-201314084037-A
Country	US
Kind code	B2
Filing date	Nov 19, 2013
Priority date	Nov 19, 2013
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

First claim

We claim:

1. A semiconductor die, comprising:
a semiconductor material having solid-state components;
a plurality of interconnects extending at least partially through the semiconductor material; and
a plurality of under-bump metal (UBM) structures, wherein individual UBM structures are electrically coupled to corresponding interconnects and the individual UBM structures comprise a first material electrically coupled to one of the interconnects, a second material electrically coupled to the first material, and a suppressant material on the second material, wherein the second material is positioned between the first material and the suppressant material, wherein the second material has a top surface above the interconnect and the suppressant material is directly on the top surface of the second material, wherein the first material is positioned between the suppressant material and at least one of the interconnects, and wherein the first material has a first electrical potential, the second material has a second electrical potential, and the suppressant material reduces a difference in electrical potential between the first and second materials.

2. The semiconductor die of claim 1 wherein the first material comprises copper, the second material comprises palladium, and the suppressant material comprises an oxide formed on the palladium.

3. The semiconductor die of claim 1 wherein the first material comprises copper, the second material comprises palladium, the semiconductor die further comprises an intermediate material of nickel between the copper and the palladium, and the suppressant material comprises an oxide formed on the palladium.

4. The semiconductor die of claim 1 wherein the first material comprises nickel, the second material comprises palladium, and the suppressant material comprises an oxide formed on the palladium.

5. The semiconductor die of claim 1 wherein:
the first material comprises copper, the second material comprises palladium, the semiconductor die further comprises an intermediate material of nickel between the copper and the palladium, and the suppressant material comprises an oxide formed on the palladium; and
the UBM structures have a cross-sectional dimension, and the copper first material has an undercut of less than 20% of the cross-sectional dimension.

6. The semiconductor die of claim 5 wherein the undercut in the copper first material is less than about 10% of the cross-sectional dimension of the UBM structure.

7. The semiconductor die of claim 1 wherein the second material is directly on the first material.

8. The semiconductor die of claim 1 wherein the suppressant material is directly on the second material.

9. The semiconductor die of claim 1 wherein the suppressant material is formed on the second material by oxidizing an upper portion of the second material.

10. The semiconductor die of claim 1 wherein the suppressant material is formed in a recessed portion of the second material.

11. The semiconductor die of claim 1 wherein the suppressant material is a conformal material layer deposited or grown over a seed structure formed on the semiconductor material.

12. The semiconductor die of claim 1 wherein an intermediate material is positioned between the first material and the second material.

13. A semiconductor die, comprising:
a semiconductor material having solid-state components;
a plurality of interconnects extending at least partially through the semiconductor material; and
a plurality of under-bump metal (UBM) structures, wherein individual UBM structures are electrically coupled to corresponding interconnects and the individual UBM structures comprise a first material electrically coupled to one of the interconnects, a second material electrically coupled to the first material, and a suppressant material directly on the second material, wherein the second material has a top surface above the interconnect and the suppressant material is on the top surface of the second material, wherein the first material is positioned between the suppressant material and at least one of the interconnects, and wherein the first material has a first electrical potential, the second material has a second electrical potential, and the suppressant material reduces a difference in electrical potential between the first and second materials.

14. The semiconductor die of claim 13 wherein the first material comprises copper, the second material comprises palladium, and the suppressant material comprises an oxide formed on the palladium.

15. The semiconductor die of claim 13 wherein the first material comprises copper, the second material comprises palladium, the semiconductor die further comprises an intermediate material of nickel between the copper and the palladium, and the suppressant material comprises an oxide formed on the palladium.

16. The semiconductor die of claim 13 wherein the first material comprises nickel, the second material comprises palladium, and the suppressant material comprises an oxide formed on the palladium.

17. The semiconductor die of claim 13 wherein:
the first material comprises copper, the second material comprises palladium, the semiconductor die further comprises an intermediate material of nickel between the copper and the palladium, and the suppressant material comprises an oxide formed on the palladium; and
the UBM structures have a cross-sectional dimension, and the copper first material has an undercut of less than 20% of the cross-sectional dimension.

18. The semiconductor die of claim 17 wherein the undercut in the copper first material is less than about 10% of the cross-sectional dimension of the UBM structure.

19. The semiconductor die of claim 13 wherein the suppressant material is formed on the second material by oxidizing an upper portion of the second material.

20. The semiconductor die of claim 13 wherein the suppressant material is formed in a recessed portion of the second material.

21. A semiconductor die, comprising:
a semiconductor material having solid-state components;
a plurality of interconnects extending at least partially through the semiconductor material; and
a plurality of under-bump metal (UBM) structures, wherein individual UBM structures are electrically coupled to corresponding interconnects and the individual UBM structures comprise a first material electrically coupled to one of the interconnects, a second material electrically coupled to the first material, and a suppressant material on the second material, wherein the second material is positioned between the first material and the suppressant material, wherein the second material has a top surface above the interconnect and the suppressant material is directly on only the top surface of the second material, wherein the first material is positioned between the suppressant material and at least one of the interconnects, and wherein the first material has a first electrical potential, the second material has a second electrical potential, and the suppressant material reduces a difference in electrical potential between the first and second materials.

22. A semiconductor die, comprising:
a semiconductor material having solid-state components;
a plurality of interconnects extending at least partially through the semiconductor material; and
a plurality of under-bump metal (UBM) structures, wherein individual UBM structures are electrically coupled to corresponding interconnects and the individual UBM structures comprise

Assignees

• Micron Technology Inc

Inventors

• Wirz Brandon P
• Gandhi Jaspreet S
• Gambee Christopher J
• Yeldandi Satish

Classifications

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/934

  Cross-sectional shape, i.e. in side view · CPC title