Semiconductor devices and methods for backside photo alignment

Patent metadata

Field	Value
Publication number	US-9741612-B2
Application number	US-201615050858-A
Country	US
Kind code	B2
Filing date	Feb 23, 2016
Priority date	May 19, 2014
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

First claim

We claim:

1. A method for aligning an electronic feature to a through-substrate via (“TSV”) extending through a semiconductor substrate on a microelectronic device, the method comprising:
forming the TSV through a semiconductor substrate, the TSV having a protruding portion that projects beyond a backside surface of the semiconductor substrate;
depositing a first passivation material over the backside surface of the semiconductor substrate and the protruding portion of the TSV;
depositing a second passivation material on the first passivation material;
removing a portion of the first passivation material and the second passivation material, thereby exposing the protruding portion of the TSV;
forming a self-aligned alignment feature having a wall around at least a portion of the TSV;
depositing a seed material on the second passivation material, wherein the seed material is electrically coupled to the TSV, and wherein the seed material conforms to the wall of the self-aligned alignment feature; and
aligning a photolithography tool to the self-aligned alignment feature.

2. The method of claim 1 wherein, after removing a portion of the first and second passivation materials, the backside surface of the TSV projects beyond the first passivation material and the second passivation material, and wherein a portion of the protruding portion of the TSV forms the wall of the self-aligned alignment feature.

3. The method of claim 1 , further comprising:
depositing a resist material on the seed material; and
creating an opening in the resist material, wherein the opening exposes the protruding portion of the TSV.

4. The method of claim 1 , further comprising:
depositing a resist material on the seed material;
creating an opening in the resist material, wherein the opening exposes the protruding portion of the TSV; and
forming an under-bump metallization (“UBM”) structure in the opening on an exposed portion of the protruding portion of the TSV.

5. The method of claim 1 wherein:
removing a portion of the first passivation material and the second passivation material comprises planarizing the first and second passivation materials until the TSV is exposed;
forming a self-aligned alignment feature includes removing a portion of the first passivation material such that a recess is formed in the first passivation material between the second passivation material and the TSV.

6. The method of claim 1 , further including creating a recess in the first passivation material that at least partially surrounds the TSV.

7. The method of claim 6 wherein the recess is formed by selectively etching the first passivation material relative to the second passivation material.

8. The method of claim 6 further comprising:
depositing a resist material on the seed material;
creating an opening in the resist material aligned with the protruding portion of the TSV; and
forming an under-bump metallization (“UBM”) structure on the seed material in the opening.

9. The method of claim 1 , wherein forming the self-aligned alignment feature includes
changing a height of the TSV, the first passivation material, or the second passivation material relative to one another such that a topographical relief defining the self-aligned alignment feature is formed.

10. The method of claim 9 , wherein the method does not include forming a fiducial at the backside of the device.

11. The method of claim 9 wherein:
changing the height includes simultaneously etching the first passivation material to a first height and the second passivation material to a second height, wherein the first height is less than the second height.

12. The method of claim 9 , wherein the method does not include forming a fiducial at the backside of the device using a separate photo-lithography process to position the fiducial at the backside of the device.

13. A method for aligning an electronic feature to a plurality of through-substrate via (“TSV”) extending through a semiconductor substrate on a microelectronic device, the method comprising:
forming the TSVs through a semiconductor substrate, the TSVs each having a protruding portion that projects beyond a backside surface of the semiconductor substrate;
depositing a first passivation material over the backside surface of the semiconductor substrate and the protruding portions of the TSVs;
depositing a second passivation material on the first passivation material;
removing a portion of the first passivation material and the second passivation material, thereby exposing the protruding portions of the TSVs;
forming a plurality of self-aligned alignment features, each having a wall around at least a portion of the corresponding TSV;
depositing a seed material on the second passivation material, wherein the seed material is electrically coupled to the TSVs, and wherein the seed material conforms to the wall of the corresponding self-aligned alignment feature; and
aligning a photolithography tool to a subset of the self-aligned alignment features, wherein the subset has a unique arrangement that is identifiable to the photolithography tool.

Assignees

• Micron Technology Inc

Inventors

• Wirz Brandon P
• Ypma Keith
• Gambee Christopher J
• Gandhi Jaspreet S
• Dowdle Kevin M
• Vasilyeva Irina
• Chao Yang
• Hacker Jon

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W46/601

  for use after dicing · CPC title

• H10W46/501

  for use before dicing · CPC title