Edge cut debond using a temporary filler material with no adhesive properties and edge cut debond using an engineered carrier to enable topography

US10403618B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10403618-B2
Application numberUS-201715711937-A
CountryUS
Kind codeB2
Filing dateSep 21, 2017
Priority dateSep 21, 2017
Publication dateSep 3, 2019
Grant dateSep 3, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a semiconductor device assembly, the method comprising: applying a filler material on a first side of a semiconductor device; positioning the first side of the semiconductor device adjacent to a substrate; applying an adhesive between an outer edge of the first side of the semiconductor device and the substrate to bond a portion of the semiconductor device to the substrate; processing on a second side of the semiconductor device, wherein processing on the second side of the semiconductor device reduces a thickness of the semiconductor device; cutting off the outer edge of the semiconductor device onto which adhesive was applied to release the semiconductor device from the substrate. 2. The method of claim 1 , wherein the adhesive is only applied to an outer edge of the semiconductor device, with respect to the semiconductor device. 3. The method of claim 1 , further comprising removing the semiconductor device from the substrate and cleaning the first side of the semiconductor device. 4. The method of claim 1 , furthering comprising removing filler material from an outer edge of the semiconductor device prior to applying the adhesive. 5. The method of claim 4 , wherein removing filler material from the outer edge of the semiconductor device further comprises removing all of the filler material within a first distance of the outer edge of the semiconductor device. 6. The method of claim 5 , wherein the first distance is five (5) mm or less. 7. The method of claim 5 , wherein a second distance from the outer edge is cut off of the semiconductor device during the cutting off the outer edge of the semiconductor device. 8. The method of claim 7 , wherein the second distance is equal to or greater than the first distance. 9. The method of claim 1 , further comprising positioning a ring on an outer edge of the semiconductor device prior to applying the filler material. 10. The method of claim 9 , further comprising applying pressure to the semiconductor device and substrate assembly prior to applying the adhesive, wherein the pressure causes the filler material to fill a space between semiconductor device, the substrate, and the ring. 11. The method of claim 10 , further comprising removing the ring from the outer edge of the semiconductor device prior to applying the adhesive. 12. A method of forming a semiconductor device assembly, the method comprising: applying a filler material onto a substrate; positioning a first side of the semiconductor device adjacent to the substrate; applying an adhesive between an outer edge the first side of the semiconductor device and the substrate to bond a portion of the semiconductor device to the substrate; processing on a second side of the semiconductor device, wherein processing on the second side of the semiconductor device reduces a thickness of the semiconductor device; cutting off the outer edge of the semiconductor device onto which adhesive was applied to release the semiconductor device from the substrate. 13. The method of claim 12 , further comprising: applying pressure to the semiconductor device and substrate assembly prior to applying the adhesive, wherein the pressure causes the filler material to fill a space between semiconductor device and the substrate; removing the semiconductor device from the substrate; and cleaning the first side of the semiconductor device. 14. The method of claim 1 , wherein the processing on the second side of the semiconductor device further comprises applying chemical mechanical planarization, grinding, or dry etching to the second side of the semiconductor device. 15. The method of claim 1 , wherein the processing on the second side of the semiconductor device further comprises forming a plurality of structures on the second side of the semiconductor device. 16. The method of claim 12 , wherein the processing on the second side of the semiconductor device further comprises applying chemical mechanical planarization, grinding, or dry etching to the second side of the semiconductor device. 17. The method of claim 12 , wherein the processing on the second side of the semiconductor device further comprises forming a plurality of structures on the second side of the semiconductor device.

Assignees

Inventors

Classifications

  • batch processes · CPC title

  • Dispositions of multiple bond pads · CPC title

  • relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

  • Cleaning, e.g. oxide removal · CPC title

  • using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates · CPC title

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Frequently asked questions

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What does patent US10403618B2 cover?
A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler …
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification H10P72/74. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 03 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).