Edge cut debond using a temporary filler material with no adhesive properties and edge cut debond using an engineered carrier to enable topography

Patent metadata

Field	Value
Publication number	US-11094684-B2
Application number	US-201916514159-A
Country	US
Kind code	B2
Filing date	Jul 17, 2019
Priority date	Sep 21, 2017
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.

First claim

What is claimed is:

1. A method of forming a semiconductor device assembly, the method comprising:
processing a top surface of a substrate to correspond to a topography of a first surface of a semiconductor device so that the top surface of the substrate includes a plurality of standoffs and a plurality of recesses with the recesses being aligned with structures on the first surface of the semiconductor device;
positioning the semiconductor device adjacent to the substrate forming a plurality of air gaps between the semiconductor device and the substrate;
applying an adhesive to bond an outer edge of the semiconductor device to the substrate;
processing the second side of the semiconductor device; and
cutting off the outer edge of the semiconductor device onto which adhesive was applied to release the semiconductor device from the substrate.

2. The method of claim 1 , further comprising applying a non-adhesive coating to the first side of the semiconductor device prior to positioning the semiconductor device adjacent to the substrate.

3. The method of claim 1 , wherein processing on the second side of the semiconductor device reduces a thickness of the semiconductor device.

4. The method of claim 1 , wherein the processing on the second side of the semiconductor device further comprises applying chemical mechanical planarization, grinding, or dry etching to the second side of the semiconductor device.

5. The method of claim 1 , wherein the processing on the second side of the semiconductor device further comprises forming a plurality of structures on the second side of the semiconductor device.

6. The method of claim 1 , further comprising removing the semiconductor device from the substrate and cleaning the first side of the semiconductor device.

7. The method of claim 1 , wherein the adhesive is a permanent adhesive.

8. A semiconductor device assembly comprising:
a semiconductor device having a first side and a second side, the first side having a first topography with a plurality of structures that protrude away from the first side;
a substrate having a top surface, the top surface having a second topography that corresponds to the first topography, the second topography including a plurality of standoffs that extend away from the top surface and a plurality of recesses, wherein the second topography is configured so the plurality of standoffs support the first side of the semiconductor device and together with the plurality of recesses create a plurality of air gaps between the top surface and the plurality of structures of the semiconductor device; and
a ring of adhesive around an outer edge of the semiconductor device that bonds the semiconductor device to the substrate to form an assembly, wherein an outer portion of the semiconductor device may be cut off the semiconductor device to remove the semiconductor device from the assembly with the substrate after the second side of the semiconductor device has been processed.

9. The assembly of claim 8 , wherein the adhesive is not present more than five mm from the outer edge of the semiconductor device.

10. The assembly of claim 8 , wherein the adhesive is a permanent adhesive.

11. The assembly of claim 8 , further comprising a non-adhesive coating applied to the first side of the semiconductor device.

12. The method of claim 1 , wherein applying an adhesive to bond an outer edge of the semiconductor device to the substrate comprises applying adhesive over a first distance from the outer edge.

13. The method of claim 12 , wherein the first distance is five millimeters or less.

14. The method of claim 12 , wherein cutting off the outer edge of the semiconductor device onto which adhesive was applied to release the semiconductor device from the substrate further comprises cutting off the outer edge of the semiconductor device at a second distance from the outer edge.

15. The method of claim 14 , wherein the second distance equals the first distance.

16. The method of claim 14 , wherein the second distance is larger than the first distance.

17. The method of claim 16 , wherein the second distance is at least one millimeter larger than the first distance.

18. The method of claim 1 , wherein the adhesive has a transition temperature of 180 degrees Celsius or above.

19. The method of claim 1 , wherein the adhesive has a transition temperature of 200 degrees Celsius or above.

20. The assembly of claim 8 , wherein the adhesive has a transition temperature of 180 degrees Celsius or above.

Assignees

• Micron Technology Inc

Inventors

• Tiwari Chandra S
• Lindenberg Tony M
• Hacker Jonathan S
• Gambee Christopher J
• Bossart Kurt J

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/01971

  Cleaning, e.g. oxide removal · CPC title

• H10W72/01904

  using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates · CPC title