On-chip reliability monitor and method
US-RE50596-E · Sep 23, 2025 · US
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Fifield John A patents
Fifield John A is listed as an inventor on 61 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Fifield John A |
| Total patents | 61 |
| First publication | Mar 24, 2015 |
| Latest publication | Sep 23, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Charge pump circuit with internal pre-charge configuration
US-10971996-B2 · Apr 6, 2021 · US
Selection circuit
US-10826489-B1 · Nov 3, 2020 · US
Charge pump circuit with internal pre-charge configuration
US-2020295653-A1 · Sep 17, 2020 · US
Ultra-low voltage level shifter
US-10707845-B2 · Jul 7, 2020 · US
Voltage boost circuit
US-10699771-B2 · Jun 30, 2020 · US
Charge pump circuit with built-in-retry
US-10673321-B2 · Jun 2, 2020 · US
Ultra-low voltage level shifter
US-2020153418-A1 · May 14, 2020 · US
High speed level translator
US-10615797-B2 · Apr 7, 2020 · US
Latching current sensing amplifier for memory array
US-10535379-B2 · Jan 14, 2020 · US
Recent patents
Latest publications not already listed above.
Voltage boost circuit
US-2019333568-A1 · Oct 31, 2019 · US
Memory array including distributed reference cells for current sensing
US-10446239-B1 · Oct 15, 2019 · US
Voltage boost circuit
US-10438652-B2 · Oct 8, 2019 · US
On-chip reliability monitor and method
US-10429434-B2 · Oct 1, 2019 · US
On-chip reliability monitor and method
US-2019265293-A1 · Aug 29, 2019 · US
Margin test for multiple-time programmable memory (MTPM) with split wordlines
US-10395752-B2 · Aug 27, 2019 · US
On-chip calibration circuit and method with half-step resolution
US-10382049-B1 · Aug 13, 2019 · US
Charge pump circuit with built-in retry
US-2019165669-A1 · May 30, 2019 · US
High speed level translator
US-2019149153-A1 · May 16, 2019 · US
Margin test for one-time programmable memory (otpm) array with common mode current source
US-2019108895-A1 · Apr 11, 2019 · US
Margin test for multiple-time programmable memory (mtpm) with split wordlines
US-2019108894-A1 · Apr 11, 2019 · US
Margin test for one-time programmable memory (OTPM) array with common mode current source
US-10255987-B1 · Apr 9, 2019 · US
Electrostatic discharge power clamp with fail-safe design
US-10224710-B2 · Mar 5, 2019 · US
High speed level translator
US-10224932-B2 · Mar 5, 2019 · US
Differential voltage generator
US-10192590-B1 · Jan 29, 2019 · US
Electrostatic discharge device with fail-safe design
US-10186860-B2 · Jan 22, 2019 · US
Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing
US-10163526-B2 · Dec 25, 2018 · US
Voltage boost circuit
US-2018350424-A1 · Dec 6, 2018 · US
Voltage boost circuit
US-10127970-B2 · Nov 13, 2018 · US
Circuit and method for detecting time dependent dielectric breakdown (tddb) shorts and signal-margin testing
US-2018233216-A1 · Aug 16, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 32 |
| Globalfoundries Inc | 24 |
| Marvell Asia Pte Ltd | 5 |
| Marvell Int Ltd | 4 |
| Fifield John A | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C17/18 | 13 |
| H02M3/07 | 13 |
| G11C11/4074 | 9 |
| G11C11/4085 | 8 |
| H02M3/158 | 8 |