Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing

Patent metadata

Field	Value
Publication number	US-10163526-B2
Application number	US-201815920677-A
Country	US
Kind code	B2
Filing date	Mar 14, 2018
Priority date	Feb 10, 2017
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

The present disclosure relates to a structure which includes a twin-cell memory which is configured to program a plurality of write operations, a current sense amplifier which is connected to the twin-cell memory and is configured to sense a current differential and latch a differential voltage based on the current differential, and at least one current source which is connected to the current sense amplifier and is configured to add an offset current to the current sense amplifier to create the differential voltage.

First claim

What is claimed:

1. A method, comprising:
skewing a sense amplifier connected to a twin-cell memory array to a known logic state;
reading an output of the sense amplifier with a plurality of wordlines connected to the twin-cell memory array turned off;
detecting a time dependent dielectric breakdown (TDDB) failure of the twin-cell memory array in response to the output of the sense amplifier being an opposite logic state of the known logic state; and
masking bits of the twin-cell memory array in response to detecting the TDDB failure.

2. The method of claim 1 , further comprising programming the twin-cell memory array for a predefined programming interval.

3. The method of claim 2 , wherein the programming the twin-cell memory array for the predefined programming interval occurs before skewing the sense amplifier to the known logic state.

4. The method of claim 2 , wherein the predefined programming interval is a time interval less than 8 milliseconds.

5. The method of claim 2 , wherein the programming the twin-cell memory array for the predefined programming interval further comprises applying a write pulse to a plurality of gates of the twin-cell memory array.

6. The method of claim 2 , further comprising verifying that an output of the twin-cell memory array is a same value as an input of the twin-cell memory array in response to not detecting the TDDB failure.

7. The method of claim 6 , further comprising masking bits of the twin-cell memory array in response to verifying that the output of the twin-cell memory array is the same value as the input of the twin-cell memory array.

8. The method of claim 1 , wherein the twin-cell memory array is included in a non-volatile one time programmable memory (OTPM).

9. The method of claim 1 , further comprising adding an offset current to a current differential of the sense amplifier to skew the sense amplifier connected to the twin-cell memory array to the known logic state.

10. The method of claim 9 , further comprising sensing the current differential and latching a differential voltage based on the current differential and the added offset current.

11. A method, comprising:
programming a twin-cell memory array for a predefined programming interval;
skewing a sense amplifier connected to the twin-cell memory array to a known logic state;
reading an output of the sense amplifier with a plurality of wordlines connected to the twin-cell memory array turned off;
detecting a time dependent dielectric breakdown (TDDB) failure of the twin-cell memory array in response to the output of the sense amplifier being an opposite logic state of the known logic state; and
masking bits of the twin-cell memory array in response to detecting the TDDB failure.

12. A method, comprising:
programming a twin-cell memory array for a predefined programming interval;
skewing a sense amplifier connected to the twin-cell memory array to a known logic state;
reading an output of the sense amplifier with a plurality of wordlines connected to the twin-cell memory array turned off;
detecting a time dependent dielectric breakdown (TDDB) failure of the twin-cell memory array in response to the output of the sense amplifier being an opposite logic state of the known logic state; and
verifying that an output of the twin-cell memory array is a same value as an input of the twin-cell memory array in response to not detecting the TDDB failure, and masking bits of the twin-cell memory array in response to verifying that the output of the twin-cell memory array is the same value as the input of the twin-cell memory array.

Assignees

• Globalfoundries Inc

Inventors

• Fifield John A
• Hunt-Schroeder Eric D
• Anand Darren L

Classifications

• G11C29/50008

  of impedance · CPC title

• G11C2029/5006

  Current · CPC title

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C17/16

  using electrically-fusible links · CPC title

• G11C29/50

  Marginal testing, e.g. race, voltage or current testing · CPC title