Differential voltage generator

Patent metadata

Field	Value
Publication number	US-10192590-B1
Application number	US-201715788289-A
Country	US
Kind code	B1
Filing date	Oct 19, 2017
Priority date	Oct 19, 2017
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

Differential voltage generators receive an initial target voltage, and provide the initial target voltage to a first offset element and a second offset element. The first offset element includes first transistors, and the second offset element includes second transistors. Each of the first transistors is capable of changing the initial target voltage by a different incremental amount to change the initial target voltage to an altered target voltage. The second transistors are capable of removing a current generated by the first transistors, thereby causing an opposite current and leaving the initial target voltage unaffected on a second output. Each of the first transistors has a corresponding second transistor that produces the same current. A first output is capable of outputting the altered target voltage, and the second output is capable of outputting the initial target voltage.

First claim

What is claimed is:

1. A differential voltage generator comprising:
a voltage input;
a first offset element and a second offset element connected to the voltage input;
a first output connected to the first offset element;
a second output connected to the second offset element and to the voltage input, wherein the voltage input is capable of receiving an initial target voltage and providing the initial target voltage to the first offset element and the second offset element, the first offset element includes first transistors, the second offset element includes second transistors, each of the first transistors is capable of changing the initial target voltage by a different incremental amount to change the initial target voltage to an altered target voltage, the second transistors are capable of removing a current generated by the first transistors thereby causing an opposite current and leaving the initial target voltage unaffected on the second output, each of the first transistors has a corresponding pair transistor in the second transistors that causes the same current flow, the first output is capable of outputting the altered target voltage, and the second output is capable of outputting the initial target voltage; and
a multiplexor connected to the first transistors and the second transistors, the multiplexor is capable of selecting, in response to selection signals, pairs of the first transistors and the second transistors that generate the same current.

2. The differential voltage generator according to claim 1 , further comprising a resistor connected between the first offset element and the second offset element, wherein the current generated by the first transistors is removed from the resistor by the current generated by the second transistors.

3. The differential voltage generator according to claim 2 , the first transistors and the second transistors generate an equal and opposite current through the resistor to prevent voltage changes caused by the first transistors from affecting the initial target voltage on the second output.

4. The differential voltage generator according to claim 1 , further comprising:
a precision current source connected to the multiplexor,
wherein the precision current source is capable of providing the selection signals to the multiplexor to select the pairs of the first transistors and the second transistors that generate the same current.

5. The differential voltage generator according to claim 1 , wherein the first transistors increment the initial target voltage in equal voltage increments from a low voltage target to a high voltage target when the first transistors change the initial target voltage to the altered target voltage.

6. The differential voltage generator according to claim 1 , further comprising a unity gain operational amplifier connected to the voltage input, the unity gain operational amplifier is capable of supplying the initial target voltage to the second output.

7. The differential voltage generator according to claim 1 , wherein the first offset element comprises a digital-to-analog converter.

8. An integrated circuit device comprising:
electronic memory cells;
electronic lines connected to the electronic memory cells; and
a charging circuit connected to the electronic lines that is capable of charging the electronic lines,
the charging circuit comprises a differential voltage generator, and the differential voltage generator comprises:
a voltage input;
a first offset element connected to the voltage input;
a second offset element connected to the voltage input;
a multiplexor connected to the first offset element and the second offset element;
a first output connected to the first offset element; and
a second output connected to the second offset element and to the voltage input,

wherein the voltage input is capable of receiving an initial target voltage and providing the initial target voltage to the first offset element and the second offset element,
wherein the first offset element includes first transistors and the second offset element includes corresponding second transistors,
wherein the multiplexor is capable of selecting pairs of the first transistors and the second transistors that generate the same current in response to selection signals,
wherein each of the first transistors is capable of changing the initial target voltage by a different incremental amount to change the initial target voltage to an altered target voltage,
wherein a current is generated by the first transistors when the first transistors change the initial target voltage to the altered target voltage,
wherein the second transistors are capable of removing the current flow generated by the first transistors by generating opposite current to leave the initial target voltage unaffected on the second output,
wherein each of the first transistors has a corresponding pair transistor in the second transistors that causes the same current flow,
wherein the first output is capable of outputting the altered target voltage, and
wherein the second output is capable of outputting the initial target voltage.

9. The integrated circuit device according to claim 8 , further comprising a resistor connected between the first offset element and the second offset element, wherein the current generated by the first transistors is removed from the resistor by the current generated by the second transistors.

10. The integrated circuit device according to claim 9 , the pairs of the first transistors and the second transistors generate an equal and opposite current through the resistor to prevent voltage changes caused by the first transistors from affecting the initial target voltage on the second output.

11. The integrated circuit device according to claim 8 , further comprising a precision current source connected to the multiplexor, wherein the precision current source is capable of providing the selection signals to the multiplexor to select the pairs of the first transistors and the second transistors that generate the same current.

12. The integrated circuit device according to claim 8 , wherein the first transistors increment the initial target voltage in equal voltage increments from a low voltage target to a high voltage target when the first transistors change the initial target voltage to the altered target voltage.

13. The integrated circuit device according to claim 8 , further comprising a unity gain operational amplifier connected to the voltage input, the unity gain operational amplifier is capable of supplying the initial target voltage to the second output.

14. The integrated circuit device according to claim 8 , wherein the first offset element comprises a digital-to-analog converter.

15. A method comprising:
receiving, by a voltage input of a differential voltage generator, an initial target voltage;
providing the initial target voltage to a first offset element and a second offset element of the differential voltage generator, wherein the first offset element includes first transistors, the second offset element includes second transistors;
changing, by the first transistors, the initial target voltage by a different incremental amount to change the initial target voltage to an altered target voltage;
removing, by the second transistors, a current generated by the first transistors thereby causing an opposite current and leaving the initial target voltage unaffected, wherein each of the first transistors has a corresponding pair transistor in the second transistors that causes the same current flow;
outputting, by a first output of the differen

Assignees

• Globalfoundries Inc

Inventors

• Fifield John A
• Hunt-Schroeder Eric

Classifications

• G11C11/4074 Primary

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G05F1/595

  semiconductor devices connected in series · CPC title

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C2207/002

  Isolation gates, i.e. gates coupling bit lines to the sense amplifier · CPC title