High speed level translator

Patent metadata

Field	Value
Publication number	US-10615797-B2
Application number	US-201916250364-A
Country	US
Kind code	B2
Filing date	Jan 17, 2019
Priority date	Aug 19, 2014
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.

First claim

What is claimed:

1. A level translator comprising:
a one-shot circuit coupled to a controllable resistor divider connected between an input voltage (VPP) and ground;
transistors coupled in parallel with a first resistor of the controllable resistor divider; and
an inverter chain coupled to the controllable resistor divider to receive a voltage level VPP 2 and having outputs to control gates of the transistors,
wherein the level translator is a 4-level translator circuit which translates the input voltage VPP to output levels VPP 2 /VPP at the outputs, a voltage stress applied to the transistors is limited to a level of a logic input signal inputted to control the controllable resistor divider, and the VPP 2 and the VPP are supplied by the controllable resistor divider to supply inverters of the inverter chain.

2. The level translator of claim 1 , wherein the one-shot circuit translates from a low voltage to a high voltage using the transistors which are arranged in parallel with the first resistor of the controllable resistor divider.

3. The level translator of claim 2 , wherein the inverter chain has outputs controlling gates of the transistors to generate an output signal oscillating between the supply voltage VPP 2 and the supply voltage VPP to provide a conduction path between an output level of the first resistor for operation between voltage levels with which the level and the ground can be translated to the voltage VPP 2 and the supply voltage VPP.

4. The level translator of claim 1 , wherein the transistors are provided with a feedback loop to improve switching performance in a direction serviced by a resistor pull up.

5. The level translator of claim 1 , wherein the controllable resistor divider comprises the first resistor and a second resistor, in series, which is enabled by a first transistor and a second transistor.

6. The level translator of claim 5 , wherein resistive values of the first resistor and second resistor are chosen to output a voltage signal V 2 IN of approximately the voltage VPP 2 when the first transistor receives a Vdd level logic input signal, and when the controllable resistor divider is disabled, the voltage signal V 2 IN is approximately the voltage VPP.

7. The level translator of claim 6 , wherein:
the one-shot circuit comprises a pull-up stack comprising a third transistor and a fourth transistor, in series, which allows conduction from the voltage VPP to the voltage signal V 2 IN;
the pull-up stack is enabled during transition of low-to-high switching; and
the pull-up stack is disabled when the low-to-high switching is complete.

8. The level translator of claim 7 , wherein the inverter chain comprises inverters connected in series.

9. The level translator of claim 8 , wherein the inverters are connected in series and establish a pull-up gate signal and its complement to the third transistor and the fourth transistor.

10. A level translator, comprising:
a controllable resistor divider connected between an input voltage (VPP) and ground, the controllable resistor divider comprising a first resistor and a second resistor;
a one-shot circuit coupled to the controllable resistor divider and comprising a pull-up stack of transistors coupled in parallel with the first resistor of resistor divider; and
an inverter chain coupled to the controllable resistor divider to receive a voltage level VPP 2 and having outputs controlling to control gates of the transistors,
wherein the level translator is a 4-level translator circuit which translates the input voltage VPP to output levels VPP 2 /VPP at the outputs, a voltage stress applied to the transistors is limited to a level of a logic input signal inputted to control the controllable resistor divider, and the VPP 2 and the VPP are supplied by the controllable resistor divider to supply inverters of the inverter chain.

11. A level translator comprising:
a one-shot circuit coupled to a controllable resistor divider and comprising connected between an input voltage (VPP) and ground;
transistors coupled in parallel with a first resistor of the controllable resistor divider; and
an inverter chain coupled to the controllable resistor divider to receive a voltage level VPP 2 and having outputs to control gates of the transistors, wherein:
the controllable resistor divider comprises the first resistor and a second resistor, in series, which is enabled by a first transistor and a second transistor,
resistive values of the first resistor and second resistor are chosen to output a voltage signal V 2 IN of approximately VPP 2 when the first transistor receives a Vdd level logic input signal, and
when the controllable resistor divider is disabled, the voltage signal V 2 IN is approximately VPP, and
wherein the level translator is a 4-level translator circuit which translates the input voltage VPP to output levels VPP 2 /VPP at the outputs, a voltage stress applied to the first transistor and the second transistor is limited to a level of a logic input signal inputted to control the controllable resistor divider, and the VPP 2 and the VPP are supplied by the controllable resistor divider to supply inverters of the inverter chain.

Assignees

• IBM

Inventors

• Fifield John A

Classifications

• H03K19/0944

  using MOSFET {or insulated gate field-effect transistors, i.e. IGFET}(H03K19/096 takes precedence) · CPC title

• H03K19/01742

  by means of a pull-up or down element · CPC title

• H03K19/01855 Primary

  synchronous, i.e. using clock signals · CPC title