Memory array including distributed reference cells for current sensing

Patent metadata

Field	Value
Publication number	US-10446239-B1
Application number	US-201816032100-A
Country	US
Kind code	B1
Filing date	Jul 11, 2018
Priority date	Jul 11, 2018
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

An array of memory cells in rows and columns with each column having a corresponding reference cell and a corresponding comparator. Each memory cell in a given row and given column is connected to a memory wordline for the row and to a memory bitline for the column. Each reference cell is connected to a reference wordline for the reference cells and to a reference bitline. Each comparator for a column has a current mirror with a reference section connected to the reference bitline for the reference cell for the column and a memory section connected to the memory bitline for the memory cells in the column. Each reference section has a current mirror node and all current mirror nodes in the array are connected to reduce mismatch and improve sensing accuracy. Voltages applied to the memory and reference wordlines are varied to provide accurate single-ended sensing, margin testing, etc.

First claim

What is claimed is:

1. A memory array comprising:
memory cells, wherein each memory cell has a first terminal connected to a common memory wordline for a row of the memory cells and a second terminal connected to a common memory bitline for a column of the memory cells;
reference cells, wherein each reference cell has a first terminal connected to a common reference wordline and a second terminal connected to a reference bitline; and
comparators, wherein each comparator comprises a current mirror comprising:
a reference section comprising a reference cell input node and a current mirror node, wherein the reference cell input node is electrically connected by a specific reference bitline to a specific reference cell and wherein a current mirror node connector electrically connects all current mirror nodes of all of the comparators; and
a memory section comprising a memory cell input node and an output voltage node, wherein the memory cell input node is electrically connected to a specific common memory bitline for a specific column of the memory cells.

2. The memory array of claim 1 ,
wherein the reference section comprises two first P-type field effect transistors and a first N-type field effect transistor electrically connected in series between a supply voltage and a pull-down node,
wherein the reference cell input node is at a junction between the two first P-type field effect transistors and the current mirror node is at a junction between one of the two first P-type field effect transistors and the first N-type field effect transistor,
wherein the memory section comprises two second P-type field effect transistors and a second N-type field effect transistor electrically connected in series between the supply voltage and the pull-down node,
wherein the memory cell input node is at a junction between the two second P-type field effect transistors and the output voltage node is at a junction between one of the two second P-type field effect transistors and the second N-type field effect transistor,
wherein gates of the two first P-type field effect transistors and the two second P-type field effect transistors are controlled by a current mirror voltage at the current mirror node, and
wherein gates of the first N-type field effect transistor and the second N-type field effect transistor are controlled by a bias voltage, and
wherein an additional N-type field effect transistor electrically connects the pull-down node to ground.

3. The memory array of claim 1 , wherein each comparator further comprises a secondary comparator circuit that compares an output voltage at the output voltage node and a current mirror voltage at the current mirror node and that outputs a digital signal at a digital output node, wherein a value of the digital signal varies depending upon a voltage differential between the current mirror voltage and the output voltage and wherein the voltage differential depends upon a current differential between currents conducted by the specific reference cell connected to the specific reference bitline and by a selected memory cell connected to the specific common memory bitline.

4. The memory array of claim 1 , wherein each comparator further comprises a secondary comparator circuit comprising:
a differential amplifier that receives, as inputs, a current mirror voltage from the current mirror node and an output voltage from the output voltage node; and
an inverter connected in series to the differential amplifier and that outputs a digital signal at a digital output node, wherein a value of the digital signal varies depending upon a voltage differential between the current mirror voltage and the output voltage and wherein the voltage differential depends upon a current differential between currents conducted by the specific reference cell connected to the specific reference bitline and by a selected memory cell connected to the specific common memory bitline.

5. The memory array of claim 1 , further comprising:
a memory wordline voltage generator that generates a memory wordline voltage;
memory wordline decoders that apply the memory wordline voltage to memory wordlines, respectively;
a reference wordline voltage generator that generates a reference wordline voltage; and
a reference wordline decoder that applies the reference wordline voltage to the reference wordline,
wherein levels of the memory wordline voltage and the reference wordline voltage are varied by the memory wordline voltage generator and the reference wordline voltage generator, respectively, depending upon operations being performed.

6. The memory array of claim 5 ,
wherein, during a read operation to determine whether a selected memory cell is unprogrammed or programmed, the reference wordline voltage generator sets the reference wordline voltage at a first level sufficient to ensure that each reference cell conducts a reference current amount that is approximately midway between a first current amount expected to be conducted by an unprogrammed memory cell and a second current amount, which is less than the first current amount, and expected to be conducted by a programmed memory cell, and
wherein, during a write operation to program the selected memory cell, the reference wordline voltage generator sets the reference wordline voltage at a second level that is different from the first level to facilitate margin testing.

7. The memory array of claim 1 , wherein each of the memory cells and the reference cells comprise a single charge trap field effect transistor.

8. The memory array of claim 1 , wherein each of the memory cells and the reference cells comprise multiple charge trap field effect transistors connected in parallel.

9. The memory array of claim 1 , wherein all reference bitlines that connect the reference cells to the comparators are all electrically connected.

10. A memory array comprising:
memory cells, wherein each memory cell has a first terminal connected to a common memory wordline for a row of the memory cells, a second terminal connected to a common memory bitline for a column of the memory cells, and a third terminal connected to ground;
reference cells, wherein each reference cell has a first terminal connected to a common reference wordline, a second terminal connected to a reference bitline, and a third terminal connected to ground;
comparators, each comparator comprising a current mirror comprising:
a reference section comprising a reference cell input node and a current mirror node, wherein the reference cell input node is electrically connected by a specific reference bitline to a specific reference cell and wherein a current mirror node connector electrically connects all current mirror nodes of all of the comparators; and
a memory section comprising a memory cell input node and an output voltage node, wherein the memory cell input node is electrically connected to a specific common memory bitline for a specific column of the memory cells;
a memory wordline voltage generator that generates a memory wordline voltage;
memory wordline decoders that apply the memory wordline voltage to memory wordlines;

a reference wordline voltage generator that generates a reference wordline voltage; and
a reference wordline decoder that applies the reference wordline voltage to the reference wordline,
wherein levels of the memory wordline voltage and the reference wordline voltage are varied by the memory wordline voltage generator and the reference wordline voltage generator, respectively, depending upon whether read, write or erase operations are being performed.

11. The memory array of claim 10 ,
wherein the reference section comprises two first P-type field effect tr

Assignees

• Globalfoundries Inc

Inventors

• Fifield John A
• Hunt-Schroeder Eric

Classifications

• G11C2029/5006

  Current · CPC title

• G11C29/50

  Marginal testing, e.g. race, voltage or current testing · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/28 Primary

  using differential sensing or reference cells, e.g. dummy cells · CPC title