Ultra-low voltage level shifter

Patent metadata

Field	Value
Publication number	US-10707845-B2
Application number	US-201816189407-A
Country	US
Kind code	B2
Filing date	Nov 13, 2018
Priority date	Nov 13, 2018
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

The present disclosure relates to a structure which includes a voltage level shifter circuit which includes a first current mirror leg circuit and a second current mirror leg circuit, the first current mirror leg circuit receives an input signal on a low voltage power supply and level shifts the input signal to a high voltage power supply which is at a greater voltage than the low voltage power supply, and the high voltage power supply is output from the second current mirror leg circuit.

First claim

What is claimed:

1. A structure comprising a voltage level shifter circuit, which includes a first current mirror leg circuit and a second current mirror leg circuit, wherein:
the first current mirror leg circuit receives an input signal on a low voltage power supply and level shifts the input signal to a high voltage power supply, which is at a greater voltage than the low voltage power supply;
the high voltage power supply is output from the second current mirror leg circuit; and
at least one of the first current mirror leg or the second current mirror leg includes a dual gate transistor.

2. The structure of claim 1 , wherein the low voltage power supply is below a threshold of the dual gate transistor.

3. The structure of claim 1 , wherein the high voltage power supply is a multiple voltage value of the low voltage power supply.

4. The structure of claim 3 , wherein the high voltage power supply exceeds a reliability of a single gate, thin oxide, low voltage transistor.

5. The structure of claim 1 , wherein:
the first current mirror leg circuit comprises a first NOR gate and a first transistor; and
the first NOR gate receives an inverted enable signal and an input signal and outputs a NETA signal.

6. A structure comprising a voltage level shifter circuit which includes a first current mirror leg circuit and a second current mirror leg circuit, wherein:
the first current mirror leg circuit receives an input signal on a low voltage power supply and level shifts the input signal to a high voltage power supply which is at a greater voltage than the low voltage power supply;
the high voltage power supply is output from the second current mirror leg circuit;
the first current mirror leg circuit comprises a first NOR gate and a first transistor;
the first NOR gate receives an inverted enable signal and an input signal and outputs a NETA signal; and
the first current mirror leg comprises a second transistor which is a dual gate, thick oxide, high voltage transistor and has a drain connected to a drain of the first transistor.

7. The structure of claim 6 , wherein the first transistor is gated with a bias signal and is the dual gate, thick oxide, high voltage transistor.

8. The structure of claim 6 , wherein:
the second current mirror leg circuit comprises a second NOR gate and a third transistor; and
the second NOR gate receives an inverted enable signal and an inverted input signal and outputs a NETB signal.

9. The structure of claim 8 , wherein the second current mirror leg circuit comprises a fourth transistor which is a dual gate, thick oxide, high voltage transistor and has a drain connected to a drain of the third transistor.

10. The structure of claim 9 , wherein the third transistor is gated with a bias signal and is the dual gate, thick oxide, high voltage transistor.

11. The structure of claim 10 , wherein the third transistor is connected to an output signal terminal.

12. A circuit, comprising:
a first current mirror leg circuit comprising a first NOR gate and a first dual gate, thick oxide, high voltage transistor; and
a second current mirror leg circuit comprising a second NOR gate and a second dual gate, thick oxide, high voltage transistor.

13. The circuit of claim 12 , further comprising a bias voltage generator and enable circuit, which receives an enable signal and generates an enable output signal and a bias signal.

14. The circuit of claim 13 , wherein the bias voltage generator and enable circuit comprise a plurality of resistors and a plurality of transistors, which generate the enable output signal and the bias signal.

15. The circuit of claim 12 , wherein the first NOR gate receives an inverted enable signal from a first inverter and an input signal and outputs a NETA signal.

16. The circuit of claim 12 , wherein the second NOR gate receives an inverted enable signal from a first inverter and an inverted input signal from a second inverter and outputs a NETB signal.

17. A method, comprising:
receiving an input signal, a bias signal, a bias voltage generator output signal, an inverted input signal, and an inverted enable signal at a voltage level shifter circuit, wherein the voltage level shifter circuit includes a first current mirror leg circuit and a second current mirror leg circuit; and
level shifting the input signal to a higher voltage than the input signal by using a differential current between the first current mirror leg circuit and the second current mirror leg circuit,
wherein
the higher voltage is a multiple voltage value of the input signal, and
at least one of the first current mirror leg circuit or the second current mirror leg circuit includes a dual gate transistor.

18. The method of claim 17 , further comprising reducing an output of the second current mirror leg circuit to a known output value in response to a power saving mode of operation being enabled.

19. The method of claim 17 , further comprising, based on an enable signal, generating the bias voltage generator output signal and the bias signal.

20. The method of claim 17 , further comprising generating the differential current between the first current mirror leg circuit and the second current mirror leg circuit based on the input signal and the inverted input signal.

21. A structure comprising a voltage level shifter circuit which includes a first current mirror leg circuit and a second current mirror leg circuit, wherein:
the first current mirror leg circuit receives an input signal on a low voltage power supply and level shifts the input signal to a high voltage power supply, which is at a greater voltage than the low voltage power supply;
the high voltage power supply is output from the second current mirror leg circuit;
the first current mirror leg circuit comprises a first transistor and a first NOR gate;
the second current mirror leg circuit comprises a second transistor and a second NOR gate;
the first transistor and the second transistor are gated with a bias signal;
the first NOR gate is connected to a source of the first transistor and receives the input signal;
the second NOR gate is connected to a source of the second transistor and receives an inverted version of the input signal;
an output of the first transistor is based on the bias signal and an output of the first NOR gate; and
an output of the second transistor is based on the bias signal and an output of the second NOR gate.

Assignees

• Marvell Int Ltd

Inventors

• Hunt-Schroeder Eric D
• Fifield John A

Classifications

• H03K3/037 Primary

  Bistable circuits · CPC title

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title