High speed level translator

Patent metadata

Field	Value
Publication number	US-10224932-B2
Application number	US-201715783044-A
Country	US
Kind code	B2
Filing date	Oct 13, 2017
Priority date	Aug 19, 2014
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.

First claim

What is claimed:

1. A level translator, comprising a level translator circuit having a one-shot circuit which translates from a low voltage to a high voltage using transistors arranged in parallel with a first resistor of a resistor divider and an inverter chain having outputs controlling gates of the transistors to generate an output signal oscillating between a voltage VPP 2 and a voltage VPP to provide a conduction path between an output of the inverter chain and an output of the first resistor for operation between voltage levels with which a voltage Vdd, and a ground can be translated to the VPP 2 and the VPP, wherein the level translator circuit is a 4-level translator circuit which translates input signals from the resistor divider to output levels VPP 2 /VPP, and the transistors have a voltage stress which is limited to the Vdd.

2. The level translator of claim 1 , wherein the transistors are provided with a feedback loop to improve switching performance.

3. The level translator of claim 1 , wherein the resistor divider comprises the first resistor and a second resistor, in series, which is enabled by a first transistor and a second transistor.

4. The level translator of claim 3 , wherein resistive values of the first resistor and second resistor are chosen to output a voltage signal V 2 IN of approximately the VPP 2 when the first transistor receives a Vdd level logic input signal, and when the resistor divider is disabled, the voltage signal V 2 IN is approximately the VPP.

5. The level translator of claim 4 , wherein:
the one-shot circuit comprises a pull-up stack comprising a third transistor and a fourth transistor, in series, which allows the conduction from the VPP to the V 2 IN;
the pull-up stack is enabled during transition of low-to-high switching; and
the pull-up stack is disabled when low-to-high switching is complete.

6. The level translator of claim 5 , wherein the inverter chain comprises inverters.

7. The level translator of claim 6 , wherein the inverters are connected in series to establish a pull-up gate signal and a complement of the pull-up gate signal to the third transistor and the fourth transistor.

8. A level translator, comprising:
a resistor divider comprising a first resistor and a second resistor with resistive values chosen to output a voltage signal V 2 IN approximately equal to a voltage signal VPP 2 when a first transistor enables the resistor divider by receiving a Vdd level logic input signal, and the resistor divider is disabled by setting the voltage signal V 2 IN to approximately a voltage signal VPP, the resistor divider having a resistive value larger for the first resistor compared to the second resistor or larger for the second resistor compared to the first resistor, and
a one-shot circuit in parallel with the resistor divider and comprising a pull-up stack, the pull-up stack is enabled during transition of low-to-high switching which increases switching speed and is disabled when low-to-high switching is complete such that a subsequent high-to low transition is unimpeded by the pull-up stack, the pull-up stack is configured to be switched off before an input node is reversed.

9. The level translator of claim 8 , wherein the one-shot circuit further comprises an inverter chain comprising inverters.

10. The level translator of claim 9 , wherein the inverters are connected in series to establish a pull-up gate signal.

11. The level translator of claim 10 , wherein the voltage signal V 2 IN is initially pulled up through the first resistor.

12. The level translator of claim 11 , wherein a pull-up to the voltage signal VPP is slower than a pull-down to the VPP 2 when the first resistor is larger than the second resistor.

13. The level translator of claim 12 , further comprising a second transistor in series with the first transistor, wherein the pull-up stack comprises a transistor.

14. The level translator of claim 13 , wherein the transistor of the pull-up stack is transitioned to a non-conducting state when the second transistor is placed in a conducting state.

15. The level translator of claim 14 , wherein the one-shot circuit does not compete with a pull-down on the voltage signal V 2 IN when the one-shot circuit is switched to a logic high.

16. The level translator of claim 15 , wherein the first resistor has a larger resistive value than the second resistor.

17. The level translator of claim 16 , wherein the second first resistor has a larger resistive value than the first resistor.

18. The level translator of claim 17 , wherein the transistor of the pull-up stack is arranged in parallel with the second resistor.

19. The level translator of claim 18 , wherein the voltage signal V 2 IN is provided between the second resistor and a ground.

20. The level translator of claim 19 , wherein a current is not provided to the inverters connected in series from the pull-up stack when the transistor of the pull-up stack is in a conducting state.

Assignees

• IBM

Inventors

• Fifield John A

Classifications

• H03K19/01855 Primary

  synchronous, i.e. using clock signals · CPC title

• H03K19/01742

  by means of a pull-up or down element · CPC title

• H03K19/0944

  using MOSFET {or insulated gate field-effect transistors, i.e. IGFET}(H03K19/096 takes precedence) · CPC title