Margin test for multiple-time programmable memory (MTPM) with split wordlines

Patent metadata

Field	Value
Publication number	US-10395752-B2
Application number	US-201715730078-A
Country	US
Kind code	B2
Filing date	Oct 11, 2017
Priority date	Oct 11, 2017
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

The present disclosure relates to a structure which includes a twin-cell memory which includes a first device and a second device and which is configured to store data which corresponds to a threshold voltage difference between the first device controlled by a first wordline and the second device controlled by a second wordline.

First claim

What is claimed:

1. A structure comprising a twin-cell memory which includes a first device and a second device and which is configured to store data which corresponds to a threshold voltage difference between the first device controlled by a first wordline and the second device controlled by a second wordline; and
a voltage read digital adjustment circuit which is configured to drive a differential voltage between a voltage level of the first wordline and a voltage level of the second wordline to a threshold offset of the twin-cell memory during a signal margin test operation,
wherein the first wordline is connected to a gate of the first device, the second wordline is connected to a gate of the second device, and the first wordline is a different wordline than the second wordline.

2. The structure of claim 1 , wherein the first device and the second device are field effect transistors (FETs) of the twin-cell memory, the structure is a multiple time programmable memory (MTPM) array, and the voltage read digital adjustment circuit receives a reference voltage, a plurality of digital adjustment control (DAC) inputs, and a margin signal.

3. The structure of claim 2 , wherein the first device and the second device are NFETs, the first device has a drain connected to a complement bitline, the gate connected to a complement wordline, and a source connected to a source line voltage node, and the second device has a drain connected to a true bitline, the gate connected to a true wordline, and a source connected to the source line voltage node.

4. The structure of claim 2 , wherein the first device and the second device are PFETs.

5. The structure of claim 1 , wherein the first wordline has a higher voltage potential than the second wordline during a true data type test of the signal margin test operation in which a cell is checked to determine if the cell passes a margined read test and masking a passing cell during subsequent write operations.

6. The structure of claim 1 , wherein the first wordline has a lower voltage potential than the second wordline during a complement data type test of the signal margin test operation in which a cell is checked to determine if the cell passes a margined read test and masking a passing cell during subsequent write operations.

7. The structure of claim 1 , wherein the first wordline is enabled with a same voltage potential as the second wordline during a non-signal margin test read operation by shorting the first wordline and the second wordline together.

8. The structure of claim 7 , wherein the same voltage potential is a threshold voltage of the twin-cell memory plus about 50-200 mV during the non-signal margin test read operation.

9. A structure comprising a multiple time programmable memory (MTPM) array which includes a plurality of twin-cell storage cells arranged in a plurality of rows and columns such that each of the plurality of twin-cell storage cells include a first NFET device and a second NFET device and are configured to store data which corresponds to a threshold voltage difference between the first device controlled by a first wordline and a second device controlled by a second wordline, and a voltage read digital adjustment circuit which is configured to drive a differential voltage between a voltage level of the first wordline and a voltage level of the second wordline to a threshold offset of the twin-cell storage cells during a signal margin test operation,
wherein the first wordline is connected to a gate of the first device, the second wordline is connected to a gate of the second device, and the first wordline is a different wordline than the second wordline.

10. The structure of claim 9 , wherein the first wordline has a higher voltage potential than the second wordline during a true data type test of the signal margin test operation in which a cell is checked to determine if the cell passes a margined read test and masking a passing cell during subsequent write operations.

11. The structure of claim 9 , wherein the first wordline has a lower voltage potential than the second wordline during a complement data type test of the signal margin test operation in which a cell is checked to determine if the cell passes a margined read test and masking a passing cell during subsequent write operations.

12. The structure of claim 9 , wherein the first wordline is enabled with a same voltage potential as the second wordline during a non-signal margin test read operation by shorting the first wordline and the second wordline together.

13. The structure of claim 12 , wherein the same voltage potential is a threshold voltage of the twin-cell memory plus about 50-200 mV during the non-signal margin test read operation.

14. A method, comprising:
programming a twin-cell memory with a write pulse;
driving a differential voltage between a voltage level of a true wordline and a voltage level of a complement wordline to a threshold offset of the twin-cell memory during a signal margin test operation;
verifying the programmed twin-cell memory by setting the true wordline to have a higher voltage than the complement wordline; and
verifying the programmed twin-cell memory by setting the true wordline to have a lower voltage than the complement wordline,
wherein the twin-cell memory comprises a first device and a second device, one of the true wordline and the complement wordline is connected to a gate of the first device, a remaining one of the true wordline and the complement wordline is connected to a gate of the second device, and the true wordline is a different wordline than the complement wordline.

15. The method of claim 14 , further comprising masking cells of the twin-cell memory which have passed verification on subsequent programming operations to protect them from a time dependent dielectric breakdown (TDDB) failure.

16. The method of claim 14 , wherein the first device comprises a first NFET device, the second device comprises a second NFET device, the first NFET device is controlled by the true wordline, the second NFET device is controlled by the complement wordline, the first device has a drain connected to a complement bitline, the gate connected to the complement wordline, and a source connected to a source line voltage node, and the second device has a drain connected to a true bitline, the gate connected to the true wordline, and a source connected to the source line voltage node.

17. The method of claim 14 , wherein a first data type is programmed by changing a threshold voltage of the first device of the twin-cell memory in response to the true wordline having the higher voltage than the complement wordline, and a second data type is programmed by changing a threshold voltage of the second device of the twin-cell memory in response to the true wordline having the lower voltage than the complement wordline.

18. The method of claim 14 , wherein the twin-cell memory comprises a first PFET device and a second PFET device.

19. The structure of claim 1 , wherein the twin-cell memory is programmed by applying programming voltages using an eFUSE.

20. The structure of claim 19 , wherein the applying the programming voltages using the eFUSE further comprises applying a write pulse voltage to gates of the twin-cell memory, grounding a bitline, and setting a voltage of a source line to be lower than the write pulse voltage.

Assignees

• Globalfoundries Inc

Inventors

• Fifield John A
• Hunt-Schroeder Eric D
• Anand Darren L

Classifications

• G11C2029/5004

  Voltage · CPC title

• G11C16/0408

  comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/0441

  comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates · CPC title

• G11C29/50004 Primary

  of threshold voltage · CPC title

• G11C16/10

  Programming or data input circuits · CPC title