Electrostatic discharge power clamp with fail-safe design

Patent metadata

Field	Value
Publication number	US-10224710-B2
Application number	US-201715815473-A
Country	US
Kind code	B2
Filing date	Nov 16, 2017
Priority date	Dec 19, 2014
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

An electrostatic discharge protection circuit includes a power clamp device, a timing circuit including a first resistor, a first capacitor that is connected with the first resistor at a first node, and a second capacitor that is connected to a second node, a logic gate including a first input connected with the first node, a second input connected with the second node, and an output connected with the power clamp device, and a decoder device connected with a first address pin and a second address pin. The first address pin and the second address pin are used to detect the power clamp device switching on at time of power on and draining current.

First claim

What is claimed is:

1. An electrostatic discharge protection circuit comprising:
a power clamp device;
a timing circuit including a first resistor, a first capacitor that is coupled with the first resistor at a first node, and a second capacitor that is coupled to a second node;
a logic gate including a first input coupled with the first node, a second input coupled with the second node, and an output coupled with the power clamp device; and
a decoder device coupled with a first address pin and a second address pin, wherein the first address pin and the second address pin are used to detect the power clamp device switching on at time of power on and draining current.

2. The electrostatic discharge protection circuit of claim 1 , wherein the first capacitor and the second capacitor each comprise at least one metal-insulator metal capacitor.

3. The electrostatic discharge protection circuit of claim 1 , wherein the first capacitor and the second capacitor each comprise at least one metal-oxide semiconductor capacitor.

4. The electrostatic discharge protection circuit of claim 1 , wherein the power clamp device switches on at the time of power on as a result of a defect of the first capacitor or the second capacitor.

5. The electrostatic discharge protection circuit of claim 1 , wherein the first address pin and the second address pin are used to determine a failure at one of the first capacitor and the second capacitor.

6. The electrostatic discharge protection circuit of claim 1 , wherein the first address pin and the second address pin are used to turn on each of a first transistor and a second transistor of the timing circuit.

7. The electrostatic discharge protection circuit of claim 6 , wherein the decoder is programmable to switch the first transistor and the second transistor of the timing circuit to a voltage that disables one of the first capacitor and the second capacitor.

8. The electrostatic discharge protection circuit of claim 1 , wherein the power clamp device is a junction transistor device.

9. The electrostatic discharge protection circuit of claim 1 , wherein the power clamp device is a rectifier device.

10. A method of fabricating an electrostatic discharge protection circuit for a chip, the method comprising:
forming, using a substrate, a first resistor, a first capacitor and a second capacitor of a timing circuit;
forming, using the substrate, a power clamp device;
forming, using the substrate, a logic gate including a first input coupled with a first node coupling the first capacitor with the first resistor, a second input coupled with a second node between the second capacitor and the first resistor, and an output coupled with the power clamp device; and
forming, using the substrate, a decoder, the decoder including a first output line and a second output line.

11. The method of claim 10 , wherein the first capacitor and the second capacitor each comprise at least one metal-insulator metal capacitor.

12. The method of claim 10 , wherein the first capacitor and the second capacitor each comprise or at least one metal-oxide semiconductor capacitor.

13. The method of claim 10 ,
wherein the first output line is coupled to a first transistor of the timing circuit, and the second output line is coupled to a second transistor of the timing circuit.

14. The method of claim 13 , wherein the decoder is coupled to a first address pin and a second address pin, and the first pin and the second pin are used to detect the power clamp device switching on at time of power on and draining current.

15. The method of claim 14 , wherein the first address pin and the second address pin are used to determine a failure at one of the first capacitor and the second capacitor, and the decoder is programmable to switch the first transistor and the second transistor of the timing circuit to a voltage that disables one of the first capacitor and the second capacitor.

16. A method of detecting a defective capacitor of an electrostatic discharge (ESD) protection circuit when power is applied to a chip and the electrostatic discharge protection circuit on the chip, the method comprising:
using a first address pin and a second address pin of a decoder of the ESD protection circuit to switch a first transistor and a second transistor of a timing circuit of the ESD protection circuit to a low impedance state;
monitoring Vnn for a current flow indicative of a defective capacitor between a first capacitor and a second capacitor of the timing circuit; and
programming the decoder to switch the first transistor and the second transistor corresponding to the defective capacitor to a voltage that disables the defective capacitor.

17. The method of claim 16 , wherein the first capacitor and the second capacitor each comprise at least one metal-insulator metal capacitor or at least one metal-oxide semiconductor capacitor.

18. The method of claim 16 , wherein the decoder the programming provides the chip to be powered on without experiencing a short to ground through the defective capacitor.

19. The method of claim 16 , wherein the power clamp device is a rectifier device.

20. The method of claim 16 , wherein the power clamp device is a junction transistor device.

Assignees

• IBM

Inventors

• Fifield John A
• Gauthier Jr Robert J
• Li Junjun

Classifications

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H01L2924/00

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H01L27/0285

  Electricity · mapped topic