On-chip reliability monitor and method

Patent metadata

Field	Value
Publication number	US-RE50596-E
Application number	US-202117488996-A
Country	US
Kind code	E1
Filing date	Sep 29, 2021
Priority date	Feb 23, 2018
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.

First claim

What is claimed is:

1. An integrated circuit chip comprising:
a substrate; and
a reliability monitor on the substrate and comprising:
a test circuit comprising a test device;
a reference circuit comprising a reference device; wherein the test device and the reference device are duplicates of a function device of the integrated circuit chip; and
a comparator circuit connected to the test circuit and the reference circuit,
wherein, when the integrated circuit chip is powered on, the reliability monitor is alternatingly operable in stress and test modes,
wherein, during each stress mode, the test device is subjected to stress conditions that emulate operating conditions of a the functional device and the reference device is unstressed, and
wherein, during each test mode, the stress conditions are removed from the test device and the comparator circuit compares a test parameter of the test device to a reference parameter of the reference device and outputs a status signal based on a difference between the test parameter and the reference parameter, and
when the status signal output by the reliability monitor switches values, a second reliability monitor on the integrated circuit chip is enabled so that the second reliability monitor alternatingly operates in stress and test modes.

2. The integrated circuit chip of claim 1 ,
wherein, when the difference between the test parameter and the reference parameter reaches a predetermined threshold amount, during a test mode, the status signal switches value,
wherein, after switching values, the status signal remains constant, and
wherein, when the integrated circuit chip is powered off and back on, the status signal is automatically reset to a last held value.

3. The integrated circuit chip of claim 1 , wherein operation of the reliability monitor is controlled by clock signals when the integrated circuit chip is powered on such that the reliability monitor periodically switches operation from a stress mode to a test mode and back.

4. The integrated circuit chip of claim 1 , wherein the comparator circuit comprises:
a current mirror;
a voltage latch; and
a status latch,
wherein the current mirror comprises:
a first leg comprising first nodes coupled to the test circuit and the voltage latch, respectively, such that, during a test mode, a first current flows through one first node to the test device and such that an analog test voltage is exhibited at another first node; and
a second leg comprising second nodes coupled to the reference circuit and the voltage latch, respectively, such that, during the test mode, a second current flows through one second node to the reference device and such that an analog reference voltage is exhibited at another second node,

wherein the voltage latch senses the analog test voltage and the analog reference voltage and converts the analog test voltage to a digital test voltage and the analog reference voltage to a digital reference voltage, and
wherein the status latch senses the digital test voltage and the digital reference voltage and outputs the status signal based on the digital test voltage and the digital reference voltage.

5. The integrated circuit chip of claim 4 , wherein the current mirror has a hysteresis function enabled by the status signal.

6. The integrated circuit chip of claim 1 ,
wherein the test circuit comprises:
an N-type field effect transistor comprising the test device;
a multiplexer; and
a plurality of P-type field effect transistors,

wherein the stress conditions bias the test device so that the test device is susceptible to hot electron injection-induced saturation drain current degradation,
wherein a source of the N-type field effect transistor is electrically connected to ground and a drain of the N-type field effect transistor is electrically connected to drains of a first P-type field effect transistor and a second P-type field effect transistor,
wherein a source of the second P-type field effect transistor is electrically connected to a drain of a third P-type field effect transistor and to a drain of a fourth P-type field effect transistor,
wherein sources of the first P-type field effect transistor, the third P-type field effect transistor and the fourth P-type field effect transistor are electrically connected to a first voltage,
wherein a gate of the N-type field effect transistor is selectively connected by the multiplexer to one of a second voltage and a third voltage that is lower than the second voltage, and
wherein the comparator circuit is electrically connected to a test node at the drains of the third P-type field effect transistor and the fourth P-type field effect transistor and at the source of the second P-type field effect transistor.

7. The integrated circuit chip of claim 1 ,
wherein the test circuit comprises an N-type field effect transistor comprising the test device, and
wherein the stress conditions bias the test device in inversion so that the test device is susceptible to positive bias temperature instability.

8. An integrated circuit chip comprising:
a substrate; and
multiple cascaded reliability monitors on the substrate,
wherein the multiple cascaded reliability monitors are essentially identical,
wherein each reliability monitor comprises: a test circuit comprising a test device; a reference circuit comprising a reference device; and a comparator circuit connected to the test circuit and the reference circuit,
wherein each reliability monitor is alternatingly operable in stress and test modes when the integrated circuit chip is powered on and when the reliability monitor is enabled,
wherein, during each stress mode, the test device is subjected to stress conditions that emulate operating conditions of a functional device and the reference device is unstressed,
wherein, during each test mode, the stress conditions are removed from the test device and the comparator circuit compares a test parameter of the test device to a reference parameter of the reference device and outputs a status signal based on a difference between the test parameter and the reference parameter,
wherein, when the difference between the test parameter and the reference parameter reaches a predetermined threshold amount, during a test mode, the status signal switches values and then remains constant, and
wherein the multiple cascaded reliability monitors comprise at least a first reliability monitor enabled by an enabled signal and a second reliability monitor coupled to the first reliability monitor such that the second reliability monitor is enabled when the status signal output from the first reliability monitor switches values.

9. The integrated circuit chip of claim 8 , wherein, when the integrated circuit chip is powered off and back on, status signals output from the reliability monitors are automatically reset to corresponding last held values.

10. The integrated circuit chip of claim 8 , wherein operation of the multiple cascaded reliability monitors is controlled by clock signals when the integrated circuit chip is powered on such that, once enabled, each reliability monitor periodically switches operation from a stress mode to the test mode and back.

11. The integrated circuit chip of claim 8 , wherein the comparator circuit comprises:
a current mirror;
a voltage latch; and
a status latch,
wherein the current mirror comprises:
a first leg comprising first nodes coupled to the test circuit and the voltage latch, respectively, such that, during the test mode, a first current flows through one first node to the test device and such that an analog test voltage is exhibited at another first node; and
a second leg comprising

Assignees

• Marvell Asia Pte Ltd

Inventors

• Fifield John A
• Hunt-Schroeder Eric
• Jacunski Mark D

Classifications

• G01R31/2879

  related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads · CPC title

• G01R31/2875

  related to heating · CPC title

• G01R31/2642 Primary

  Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests · CPC title

• G01R31/2856 Primary

  Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title

• G01R31/2851 Primary

  Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801) · CPC title