Semiconductor memory device
US-2024315058-A1 · Sep 19, 2024 · US
using auxiliary members, e.g. aids for protecting the bonding area
using auxiliary members, e.g. aids for protecting the bonding area · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10W80/211 |
| Official title | {using auxiliary members, e.g. aids for protecting the bonding area} |
| Display label | using auxiliary members, e.g. aids for protecting the bonding area |
| Total patents | 1,338 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is growing.
| Year | Patents |
|---|---|
| 2015 | 26 |
| 2016 | 29 |
| 2017 | 41 |
| 2018 | 46 |
| 2019 | 58 |
| 2020 | 120 |
| 2021 | 161 |
| 2022 | 198 |
| 2023 | 206 |
| 2024 | 188 |
| 2025 | 217 |
| 2026 | 48 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Semiconductor processing tool and methods of operation
US-2024084455-A1 · Mar 14, 2024 · US
Method for producing an electronic device
US-9769931-B2 · Sep 19, 2017 · US
Semiconductor-on-insulator with back side strain inducing material
US-9748272-B2 · Aug 29, 2017 · US
3D Chip-On-Wafer-On-Substrate Structure With Via Last Process
US-2017005027-A1 · Jan 5, 2017 · US
System on integrated chips and methods of forming same
US-9524959-B1 · Dec 20, 2016 · US
Semiconductor devices
US-9520361-B2 · Dec 13, 2016 · US
Method of fabricating an electronic package
US-2016358885-A1 · Dec 8, 2016 · US
Semiconductor-On-Insulator With Back Side Heat Disspation
US-2016359002-A1 · Dec 8, 2016 · US
Method for bonding substrates
US-2016358881-A1 · Dec 8, 2016 · US
Semiconductor Package for Thermal Dissipation
US-2016358894-A1 · Dec 8, 2016 · US
Vertically integrated wafers with thermal dissipation
US-9508685-B2 · Nov 29, 2016 · US
Semiconductor package assembly and method for forming the same
US-2016343695-A1 · Nov 24, 2016 · US
Semiconductor-on-insulator with back side strain topology
US-9466719-B2 · Oct 11, 2016 · US
Methods and Devices for Fabricating and Assembling Printable Semiconductor Elements
US-2016293794-A1 · Oct 6, 2016 · US
Methods and Devices for Fabricating and Assembling Printable Semiconductor Elements
US-2016284544-A1 · Sep 29, 2016 · US
3D chip-on-wafer-on-substrate structure with via last process
US-9449837-B2 · Sep 20, 2016 · US
Methods and devices for fabricating and assembling printable semiconductor elements
US-9450043-B2 · Sep 20, 2016 · US
Chip support substrate, chip support method, three-dimensional integrated circuit, assembly device, and fabrication method of three-dimensional integrated circuit
US-9449948-B2 · Sep 20, 2016 · US
Semiconductor package for thermal dissipation
US-9449947-B2 · Sep 20, 2016 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10W80/211?
- CPC H10W80/211 is the Cooperative Patent Classification code for “using auxiliary members, e.g. aids for protecting the bonding area.”
- How many patents are filed under CPC H10W80/211 (using auxiliary members, e.g. aids for protecting the bonding area)?
- Our database includes 1,338 publications tagged with this CPC code.
- Is patent activity under CPC H10W80/211 growing?
- Publication counts under this code: 188 in 2024 vs 217 in 2025 (latest complete years).