Semiconductor-on-insulator with back side strain inducing material

Patent metadata

Field	Value
Publication number	US-9748272-B2
Application number	US-201213452836-A
Country	US
Kind code	B2
Filing date	Apr 21, 2012
Priority date	Jul 15, 2009
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Embodiments of the present invention provide for the application of strain inducing layers to enhance the mobility of transistors formed on semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a strain inducing material is deposited on the excavated insulator region. The strain inducing material interacts with the pattern of excavated insulator such that a single layer provides both tensile and compressive stress to p-channel and n-channel transistors, respectively. In alternative embodiments, the entire substrate is removed before forming the strain inducing material.

First claim

What is claimed is:

1. A method of fabricating an integrated circuit, the method comprising the steps of:
forming a plurality of active devices in an active layer of a semiconductor-on-insulator wafer, the active devices including n-channel and p-channel transistors, each active device having a channel;
wherein the plurality of active devices are predominantly n-channel transistors or predominantly p-channel transistors;
removing a substrate material from a substrate layer disposed on a back side of said semiconductor-on-insulator wafer; and
forming a single layer of strain inducing material proximate or in a portion of the channel of at least one n-channel transistor and at least one p-channel transistor.

2. The method of claim 1 , further comprising the step of selecting one of a material or an arrangement of the strain inducing material that provides an increase in a mobility of charge carriers in the n-channel transistor or the p-channel transistor.

3. The method of claim 1 , further comprising the step of removing an insulator material from said back side of said semiconductor-on-insulator wafer before forming the strain inducing material.

4. The method of claim 1 , wherein the step of forming the strain inducing material forms variant configurations on the back side of the semiconductor-on-insulator wafer.

5. The method of claim 1 , wherein the step of forming the strain inducing material selectively forms at least one of a mechanical tensile strain inducing material and a compressive strain inducing material.

6. The method of claim 1 , wherein a material to form the strain inducing material is selected from the group comprising: silicon nitride, aluminum nitride, and diamond-like carbon.

7. The method of claim 6 , further comprising the step of changing conditions under which the material is deposited to create a compressive or tensile strain in the strain inducing material.

8. The method of claim 1 , further comprising the step of arranging the strain inducing material in different patterns that create bi-axial strain or uni-axial strain in a direction parallel or perpendicular to the flow of charge carriers.

9. The method of claim 1 , further comprising the step of arranging the strain inducing material in patterns selected from the group comprising: a pattern that surrounds a gate of the active device, a pattern that surrounds the gate of the active device that has a large ratio of width over length, a striped pattern that transverses, and a strip pattern formed along a side of the gate.

10. The method of claim 1 , further comprising the step of arranging the strain inducing material for a subset of active devices in the active layer.

11. The method of claim 1 , further comprising the step of using a material for the strain inducing material that has a thermal conductivity greater than 50 W/m*K.

12. An integrated circuit product created in accordance with the method of claim 1 .

13. A method for fabricating a semiconductor device, the method comprising the steps of:
forming a plurality of active devices in an active layer of a semiconductor-on-insulator wafer, the active devices including n-channel and p-channel transistors, each active device having a channel and a gate;
wherein the plurality of active devices are predominantly n-channel transistors or predominantly p-channel transistors; and
forming a single layer of strain inducing material after the step of forming the active devices, the strain inducing material being situated proximate or in the channel of at least one n-channel and at least one p-channel transistor and on an opposite side of the channel from the gate.

14. The method of claim 13 , further comprising the step of removing an insulator material from a back side of said semiconductor-on-insulator wafer.

15. The method of claim 14 , wherein the step of removing the insulator material removes the insulator material from said back side of said semiconductor-on-insulator wafer before forming the strain inducing material.

16. The method of claim 13 , wherein the step of forming the strain inducing material forms variant configurations on a back side of the semiconductor-on-insulator wafer.

17. The method of claim 13 , wherein the step of forming the strain inducing material selectively forms at least one of a mechanical tensile strain inducing material and a compressive strain inducing material.

18. The method of claim 13 , wherein a material to form the strain inducing material is selected from the group comprising: silicon nitride, aluminum nitride, and diamond-like carbon.

19. A semiconductor device product created in accordance with the method of claim 13 .

Assignees

• Nygaard Paul A
• Molin Stuart B
• Stuber Michael A
• Qualcomm Inc

Inventors

• Nygaard Paul A
• Molin Stuart B
• Stuber Michael A

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W72/07551

  characterised by changes in properties of the bond wires during the connecting · CPC title