Semiconductor devices

Patent metadata

Field	Value
Publication number	US-9520361-B2
Application number	US-201514937406-A
Country	US
Kind code	B2
Filing date	Nov 10, 2015
Priority date	Nov 13, 2014
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive structure on the first conductive structure. The semiconductor device includes first and second metal-diffusion-blocking layers on respective sidewalls of the first and second conductive structures. The semiconductor device includes an insulating layer between the first and second metal-diffusion-blocking layers. Moreover, the semiconductor device includes a metal-diffusion-shield pattern in the insulating layer and spaced apart from the first conductive structure.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a first insulating interlayer on the substrate;
a first conductive pattern structure in the first insulating interlayer, the first conductive pattern structure protruding upwardly beyond a top surface of the first insulating interlayer;
a first diffusion blocking insulation layer on the first insulating interlayer, the first diffusion blocking insulation layer on an upper portion of a sidewall of the first conductive pattern structure that protrudes beyond the first insulating interlayer;
a first bonding layer on the first diffusion blocking insulation layer, the first bonding layer on the upper portion of the sidewall of the first conductive pattern structure that protrudes beyond the first insulating interlayer;
a first shield pattern in the first bonding layer, the first shield pattern being spaced apart from the first conductive pattern structure and surrounding the first conductive pattern structure;
a second bonding layer on the first bonding layer and the first shield pattern;
a second diffusion blocking insulation layer on the second bonding layer;
a second insulating interlayer on the second diffusion blocking insulation layer;
a second conductive pattern structure in the second insulating interlayer, the second diffusion blocking insulation layer, and the second bonding layer, the second conductive pattern structure contacting a top surface of the first conductive pattern structure; and
a second shield pattern in the second bonding layer, the second shield pattern being spaced apart from the second conductive pattern structure and surrounding the second conductive pattern structure.

2. The semiconductor device of claim 1 , wherein the first and second shield patterns contact each other.

3. The semiconductor device of claim 1 ,
wherein the first conductive pattern structure comprises:
a first barrier layer pattern on sidewalls of the first insulating interlayer, the first diffusion blocking insulation layer, and the first bonding layer, respectively; and
a first conductive pattern,

wherein the first barrier layer pattern is on a sidewall and a bottom surface of the first conductive pattern,
wherein the second conductive pattern structure comprises:
a second barrier layer pattern on sidewalls of the second insulating interlayer, the second diffusion blocking insulation layer, and the second bonding layer, respectively; and
a second conductive pattern, and

wherein the second barrier layer pattern is on a sidewall and a top surface of the second conductive pattern.

4. The semiconductor device of claim 3 , wherein the first and second barrier layer patterns and the first and second shield patterns each comprise a metal, a metal nitride, or a metal alloy.

5. The semiconductor device of claim 3 , wherein each of the first and second conductive patterns comprises copper, aluminum, tungsten, and/or nickel.

6. The semiconductor device of claim 1 , further comprising:
a third insulating interlayer between the substrate and the first insulating interlayer, the third insulating interlayer comprising a third conductive pattern structure therein that contacts the first conductive pattern structure; and
a fourth insulating interlayer on the second insulating interlayer, the fourth insulating interlayer comprising a fourth conductive pattern structure therein that contacts the second conductive pattern structure.

7. The semiconductor device of claim 6 , further comprising:
a first etch stop layer between the first and third insulating interlayers, the first etch stop layer on a lower portion of the sidewall of the first conductive pattern structure; and
a second etch stop layer between the second and fourth insulating interlayers, the second etch stop layer on an upper portion of a sidewall of the second conductive pattern structure.

8. The semiconductor device of claim 1 , wherein the first conductive pattern structure contacts the second bonding layer, and the second conductive pattern structure contacts the first bonding layer.

9. The semiconductor device of claim 1 , wherein the first shield pattern comprises a plurality of first shield patterns spaced apart from each other in the first bonding layer, and the second shield pattern comprises a plurality of second shield patterns spaced apart from each other in the second bonding layer.

10. The semiconductor device of claim 9 , wherein at least one of the plurality of first shield patterns and at least one of the plurality of second shield patterns contact each other.

11. A semiconductor device, comprising:
a substrate;
a first insulating interlayer on the substrate;
a first conductive connector in the first insulating interlayer, the first conductive connector protruding upwardly beyond a top surface of the first insulating interlayer;
a first diffusion blocking layer on the first insulating interlayer, the first diffusion blocking layer on an upper portion of a sidewall of the first conductive connector that protrudes beyond the first insulating interlayer;
a first bonding layer on the first diffusion blocking layer, the first bonding layer on the upper portion of the sidewall of the first conductive connector that protrudes beyond the first insulating interlayer;
a first shield pattern in the first bonding layer and the first diffusion blocking layer, the first shield pattern being spaced apart from and defining a perimeter around the first conductive connector;
a second bonding layer on the first bonding layer and the first shield pattern;
a second diffusion blocking layer on the second bonding layer;
a second insulating interlayer on the second diffusion blocking layer;
a second conductive connector in the second insulating interlayer, the second diffusion blocking layer, and the second bonding layer, the second conductive connector contacting a top surface of the first conductive connector; and
a second shield pattern in the second bonding layer and the second diffusion blocking layer, the second shield pattern being spaced apart from and defining a perimeter around the second conductive connector.

12. The semiconductor device of claim 11 , wherein the first and second shield patterns contact each other.

13. The semiconductor device of claim 11 , wherein the first conductive connector contacts the second bonding layer, and the second conductive connector contacts the first bonding layer.

14. The semiconductor device of claim 11 , wherein the first shield pattern comprises a plurality of first shield patterns spaced apart from each other in the first bonding layer and the first diffusion blocking layer, and the second shield pattern comprises a plurality of second shield patterns spaced apart from each other in the second bonding layer and the second diffusion blocking layer.

15. The semiconductor device of claim 14 , wherein at least one of the plurality of first shield patterns and at least one of the plurality of second shield patterns contact each other.

16. A semiconductor device comprising:
a substrate;
a first conductive structure on the substrate;
a second conductive structure on the first conductive structure;
an insulating interlayer on a sidewall of the first conductive structure, the insulating interlayer including an oxide;
first and second metal-diffusion-blocking layers on respective sidewalls of the first and second conductive structures, the first and second metal-diffusion-blocking layers including a nitride, and the first metal-diffusion-blocking layer being on the insulating interlayer;
an insulating la

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Pil-Kyu
• Kim Seok-Ho
• Kim Tae-Yeong
• Kim Hyo-Ju
• Park Byung-Lyul
• Jang Joo-Hee
• Chun Jin-Ho

Classifications

• H10W80/701

  characterised by the pads after the direct bonding · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title