Semiconductor package for thermal dissipation

Patent metadata

Field	Value
Publication number	US-9449947-B2
Application number	US-201414321365-A
Country	US
Kind code	B2
Filing date	Jul 1, 2014
Priority date	Jul 1, 2014
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first package comprising:
a first semiconductor die surrounded by an encapsulant; and
vias through the encapsulant and laterally removed from the first semiconductor die; and

a first substrate bonded to the first package with a first external connection and a second external connection, wherein the second external connection comprises a different material than the first external connection, wherein the first external connection is a solder bump and the second external connection is a copper block.

2. The semiconductor device of claim 1 , wherein the second external connection is located completely beneath the first semiconductor die.

3. The semiconductor device of claim 1 , wherein the second external connection is located partially beneath the first semiconductor die.

4. The semiconductor device of claim 1 , wherein the second external connection is located laterally removed from the first semiconductor die in a top down view.

5. The semiconductor device of claim 1 , wherein the first package is an integrated fan out package.

6. A semiconductor device comprising:
a first package, the first package comprising:
an encapsulant;
through vias extending through the encapsulant;
a semiconductor die separate from the through vias and located within the encapsulant, wherein the through vias have a first thickness that is at least as great as a thickness of the semiconductor die; and

a substrate bonded to the first package through first connectors and second connectors, wherein the first connectors are located over the semiconductor die and conduct heat faster than the second connectors.

7. The semiconductor device of claim 6 , wherein the second connectors are solder bumps and the first connectors are copper blocks.

8. The semiconductor device of claim 6 , wherein the second connectors are solder bumps and the first connectors are copper balls.

9. The semiconductor device of claim 6 , wherein the first package is an integrated fan out package.

10. The semiconductor device of claim 6 , further comprising slots located within the first connectors.

11. The semiconductor device of claim 6 , wherein the first connectors have a higher thermal conductivity than the second connectors.

12. The semiconductor device of claim 6 , further comprising a second package bonded to the first package on an opposite side of the first package than the substrate.

13. A semiconductor device comprising:
a first package comprising:
a first semiconductor die surrounded by an encapsulant; and
vias through the encapsulant and laterally removed from the first semiconductor die; and

a first substrate bonded to the first package with a first external connection and a second external connection, wherein the second external connection comprises a different material than the first external connection, wherein the second external connection is located completely beneath the first semiconductor die.

14. The semiconductor device of claim 13 , wherein the first external connection is a solder bump and the second external connection is a copper block.

15. The semiconductor device of claim 13 , wherein the first external connection is a solder bump and the second external connection is a copper ball.

16. The semiconductor device of claim 13 , wherein the first external connection is a solder bump and the second external connection is a copper foil.

17. The semiconductor device of claim 13 , wherein the first package is an integrated fan out package.

18. The semiconductor device of claim 13 , further comprising slots located within the second external connection.

19. The semiconductor device of claim 13 , wherein the first external connection has a lower thermal conductivity than the second external connection.

20. The semiconductor device of claim 13 , further comprising a second substrate bonded to the first package on an opposite side of the first package than the first substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Jeng Shin-Puu
• Yeh Der-Chyang
• Chen Hsien-Wei
• Hsieh Cheng-Chieh
• Chiu Ming-Yen

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/721

  of bump connectors · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title