Chip support substrate, chip support method, three-dimensional integrated circuit, assembly device, and fabrication method of three-dimensional integrated circuit

Patent metadata

Field	Value
Publication number	US-9449948-B2
Application number	US-201314427232-A
Country	US
Kind code	B2
Filing date	Sep 13, 2013
Priority date	Sep 23, 2012
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

The present invention relates to a chip support substrate including a lyophilic region 4 that is formed on the substrate and that absorbs a chip 3 A, and an electrode 6 that is formed on the substrate and in the lyophilic region and that generates electrostatic force in the chip, and to a chip support method including the steps of arranging the chip onto the lyophilic region of the chip support substrate with a liquid 15 , the chip support substrate comprising the lyophilic region that is formed on the substrate, and the electrode that is formed on the substrate and in the lyophilic region, and generating the electrostatic force in the chip corresponding to the electrode by applying a voltage to the electrode.

First claim

The invention claimed is:

1. A chip support substrate comprising:
a lyophilic region that is formed on the substrate and that absorbs a chip; and
a cathode and an anode that are formed on the substrate and in the lyophilic region, that generate electrostatic force in the chip by applying a negative voltage to the cathode and applying a positive voltage to the anode.

2. The chip support substrate according to claim 1 ,
wherein the lyophilic region includes a plurality of lyophilic regions that respectively absorb a plurality of the chips, and
wherein the cathode and the anode are formed in each of the plurality of lyophilic regions.

3. The chip support substrate according to claim 1 ,
wherein the substrate is formed by a semiconductor, glass, ceramic, plastic or an interposer substrate.

4. The chip support substrate according to claim 1 ,
wherein the cathode includes a plurality of cathodes, the anode includes a plurality of anodes, and
wherein, in the electrode, arrangement of the plurality of anodes and the plurality of cathodes is not fixed.

5. The chip support substrate according to claim 1 , wherein the lyophilic region absorbs the chip by surface tension of a liquid dropped on the lyophilic region.

6. A chip support substrate comprising:
a lyophilic region that is formed on the substrate and that absorbs a chip; and
an electrode that is formed on the substrate and in the lyophilic region, that generates electrostatic force in the chip, and that comprises a cathode and an anode,
wherein the lyophilic region is formed by an insulation film.

7. A chip support substrate comprising:
a lyophilic region that is formed on the substrate and that absorbs a chip; and
an electrode that is formed on the substrate and in the lyophilic region, that generates electrostatic force in the chip, and that comprises a cathode and an anode,
wherein a region where the lyophilic region is not arranged on the substrate comprises a region having a lyophilic property lower than that of the lyophilic region.

8. A chip support substrate comprising:
a lyophilic region that is formed on the substrate and that absorbs a chip; and
an electrode that is formed on the substrate and in the lyophilic region, that generates electrostatic force in the chip, and that comprises a cathode and an anode,
wherein the cathode includes a plurality of cathodes, the anode includes a plurality of anodes, and
wherein, in the lyophilic region, the plurality of cathodes and the plurality of anodes are disposed in a lattice shape along a first direction that is in parallel to an upper surface of the substrate and a second direction that is in parallel to the upper surface and that crosses the first direction.

9. A three-dimensional integrated circuit comprising:
the chip support substrate comprising a lyophilic region that is formed on the substrate and that absorbs a chip, and an electrode that is formed on the substrate and in the lyophilic region, that generates electrostatic force in the chip, and that comprises a cathode and an anode;
a chip that is laminated on the lyophilic region; and
another chip of one layer or more that is laminated on the chip.

10. The three-dimensional integrated circuit according to claim 9 ,
wherein the chip comprises another lyophilic region that absorbs the another chip on its upper surface, and other cathode and other anode that are formed on the upper surface of the chip and in the another lyophilic region and that generate electrostatic force in the another chip.

11. A chip support method comprising the steps of:
arranging a chip via a liquid onto a lyophilic region of a chip support substrate comprising the lyophilic region that is formed on the substrate, and an electrode that is formed on the substrate and in the lyophilic region and that comprise a cathode and an anode; and generating electrostatic force in the chip corresponding to the electrode by applying a voltage to the electrode.

12. The chip support method according to claim 11 ,
wherein the lyophilic region includes a plurality of the lyophilic regions that respectively absorb a plurality of the chips,
wherein the electrode is formed in each of the plurality of lyophilic regions, and
wherein the step of arranging the chip comprises the step of arranging each of the plurality of chips onto each of the plurality of lyophilic regions via the liquids.

13. The chip support method according to claim 11 , further comprising the step of
allowing the chip to be absorbed to the lyophilic region.

14. The chip support method according to claim 11 ,
wherein the step of generating the electrostatic force comprises the step of generating the electrostatic force in such a manner that a center of the chip is arranged between the cathode and the anode, by supplying a voltage to the cathode and the anode while there is the liquid.

15. The chip support method according to claim 11 ,
wherein the step of generating the electrostatic force comprises the step of generating the electrostatic force in such a manner that the chip is absorbed to the chip support substrate.

16. The chip support method according to claim 11 , further comprising the step of laminating another chip on the chip while the chip is absorbed to the chip support substrate.

17. The chip support method according to claim 11 , further comprising the steps of:
transferring the chip that is absorbed to the chip support substrate to another substrate; and
transferring the chip that is transferred to the another substrate to a semiconductor wafer.

18. The chip support method according to claim 11 , further comprising the step of
transferring the chip that is absorbed to the chip support substrate onto a semiconductor wafer.

19. The chip support method according to claim 11 ,
wherein a region where the lyophilic region is not arranged on the substrate comprises a region having a lyophilic property lower than that of the lyophilic region.

20. The chip support method according to claim 19 , further comprising the step of
removing the region having the lower lyophilic property.

21. A fabrication method of a three-dimensional integrated circuit comprising the chip support method according to claim 11 .

22. An assembly device comprising:
a stage for mounting a chip support substrate comprising a lyophilic region that is formed on the substrate and a cathode and an anode that are formed on the substrate and in the lyophilic region;
a droplet supply unit for supplying a droplet onto the lyophilic region;
a carrier robot for supplying a chip onto the droplet supplied onto the lyophilic region; and
a power source unit for supplying a voltage to the electrode in such a manner that electrostatic force is generated in the chip,
wherein the electrostatic force is generated in the chip by applying a negative voltage to the cathode and applying a positive voltage to the anode.

Assignees

• Univ Tohoku

Inventors

• Koyanagi Mitsumasa
• Tanaka Tetsu
• Fukushima Takafumi

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/073

  of die-attach connectors · CPC title